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euro-adc-65m-14b-40cha-gw
Commit 0ee470e5 authored by Dave Newbold's avatar Dave Newbold
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Changes for timing interfaces, upstream and downstream

parent c6704416
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Showing with 207 additions and 145 deletions
boards/pc051a/base_fw/synth/firmware/hdl/top_pc051a.vhd
View file @ 0ee470e5
...@@ -45,12 +45,12 @@ entity top is port( ...@@ -45,12 +45,12 @@ entity top is port(
adc_d_n: in std_logic_vector(N_CHAN - 1 downto 0); adc_d_n: in std_logic_vector(N_CHAN - 1 downto 0);
analog_scl: out std_logic; analog_scl: out std_logic;
analog_sda: inout std_logic; analog_sda: inout std_logic;
sync_a_p: inout std_logic; sync_in_p: in std_logic;
sync_a_n: inout std_logic; sync_in_n: in std_logic;
sync_b_p: inout std_logic; trig_in_p: in std_logic;
sync_b_n: inout std_logic; trig_in_n: in std_logic;
-- sync_c_p: inout std_logic; trig_out_p: out std_logic;
-- sync_c_n: inout std_logic; trig_out_n: out std_logic;
clk_pll_p: out std_logic; clk_pll_p: out std_logic;
clk_pll_n: out std_logic clk_pll_n: out std_logic
); );
...@@ -134,12 +134,12 @@ begin ...@@ -134,12 +134,12 @@ begin
analog_scl => analog_scl, analog_scl => analog_scl,
analog_sda_o => analog_sda_o, analog_sda_o => analog_sda_o,
analog_sda_i => analog_sda, analog_sda_i => analog_sda,
sync_a_p => sync_a_p, sync_in_p => sync_a_p,
sync_a_n => sync_a_n, sync_in_n => sync_a_n,
sync_b_p => sync_b_p, trig_in_p => sync_b_p,
sync_b_n => sync_b_n, trig_in_n => sync_b_n,
-- sync_c_p => sync_c_p, trig_out_p => sync_c_p,
-- sync_c_n => sync_c_n, trig_out_n => sync_c_n,
clk_pll_p => clk_pll_p, clk_pll_p => clk_pll_p,
clk_pll_n => clk_pll_n clk_pll_n => clk_pll_n
); );
......
boards/pc051a/base_fw/synth/firmware/ucf/pc051a.tcl
View file @ 0ee470e5
...@@ -100,12 +100,12 @@ set_property PACKAGE_PIN W11 [get_ports {clk40_p}] ...@@ -100,12 +100,12 @@ set_property PACKAGE_PIN W11 [get_ports {clk40_p}]
set_property PACKAGE_PIN W12 [get_ports {clk40_n}] set_property PACKAGE_PIN W12 [get_ports {clk40_n}]
set_property IOSTANDARD LVDS_25 [get_ports {sync_*}] set_property IOSTANDARD LVDS_25 [get_ports {sync_*}]
set_property PACKAGE_PIN J15 [get_ports {sync_a_p}] set_property PACKAGE_PIN J15 [get_ports {trig_out_p}]
set_property PACKAGE_PIN H15 [get_ports {sync_a_n}] set_property PACKAGE_PIN H15 [get_ports {trig_out_n}]
set_property PACKAGE_PIN G17 [get_ports {sync_b_p}] set_property PACKAGE_PIN G17 [get_ports {trig_in_p}]
set_property PACKAGE_PIN G18 [get_ports {sync_b_n}] set_property PACKAGE_PIN G18 [get_ports {trig_in_n}]
#set_property PACKAGE_PIN H17 [get_ports {sync_c_p}] set_property PACKAGE_PIN H17 [get_ports {sync_in_p}]
#set_property PACKAGE_PIN H18 [get_ports {sync_c_n}] set_property PACKAGE_PIN H18 [get_ports {sync_in_n}]
false_path {sync_*} eth_refclk false_path {sync_*} eth_refclk
set_property IOSTANDARD LVDS_25 [get_ports {clk_pll_*}] set_property IOSTANDARD LVDS_25 [get_ports {clk_pll_*}]
......
boards/pc051b/base_fw/synth/firmware/hdl/top_pc051b.vhd
View file @ 0ee470e5
...@@ -32,9 +32,9 @@ entity top is port( ...@@ -32,9 +32,9 @@ entity top is port(
clkgen_rstn: out std_logic; -- si5345 RST clkgen_rstn: out std_logic; -- si5345 RST
clk_p: in std_logic; -- clk from si5345 clk_p: in std_logic; -- clk from si5345
clk_n: in std_logic; clk_n: in std_logic;
t_sync: in std_logic; -- IO via timing interface sync_in: in std_logic; -- IO via timing interface
t_trig: in std_logic; trig_in: in std_logic;
t_busy: out std_logic; trig_out: out std_logic;
adc_d_p: in std_logic_vector(63 downto 0); -- ADC serial input data adc_d_p: in std_logic_vector(63 downto 0); -- ADC serial input data
adc_d_n: in std_logic_vector(63 downto 0) adc_d_n: in std_logic_vector(63 downto 0)
); );
...@@ -106,9 +106,9 @@ begin ...@@ -106,9 +106,9 @@ begin
clkgen_rstn => clkgen_rstn, clkgen_rstn => clkgen_rstn,
clk_p => clk_p, clk_p => clk_p,
clk_n => clk_n, clk_n => clk_n,
t_sync => t_sync, sync_in => sync_in,
t_trig => t_trig, trig_in => trig_in,
t_busy => t_busy, trig_out => trig_out,
adc_d_p => adc_d_p, adc_d_p => adc_d_p,
adc_d_n => adc_d_n adc_d_n => adc_d_n
); );
......
boards/pc051b/base_fw/synth/firmware/ucf/pc051b.tcl
View file @ 0ee470e5
...@@ -100,15 +100,15 @@ set_property PACKAGE_PIN W11 [get_ports {clk_p}] ...@@ -100,15 +100,15 @@ set_property PACKAGE_PIN W11 [get_ports {clk_p}]
set_property PACKAGE_PIN W12 [get_ports {clk_n}] set_property PACKAGE_PIN W12 [get_ports {clk_n}]
# Bank 15, 2V5 # Bank 15, 2V5
set_property IOSTANDARD LVCMOS25 [get_ports {t_sync t_trig}] set_property IOSTANDARD LVCMOS25 [get_ports {sync_in trig_in}]
set_property PACKAGE_PIN J16 [get_ports {t_sync}] set_property PACKAGE_PIN J16 [get_ports {sync_in}]
set_property PACKAGE_PIN M17 [get_ports {t_trig}] set_property PACKAGE_PIN M17 [get_ports {trig_in}]
false_path {t_sync t_trig} eth_refclk false_path {sync_in trig_in} eth_refclk
# Bank 14, 3V3 # Bank 14, 3V3
set_property IOSTANDARD LVCMOS33 [get_ports t_busy] set_property IOSTANDARD LVCMOS33 [get_ports trig_out]
set_property PACKAGE_PIN Y19 [get_ports {t_busy}] set_property PACKAGE_PIN Y19 [get_ports {trig_out}]
false_path {t_busy} eth_refclk false_path {trig_out} eth_refclk
# Bank 13,15,16, 2V5 / 14, 3V3 (bits 61, 63) # Bank 13,15,16, 2V5 / 14, 3V3 (bits 61, 63)
set_property IOSTANDARD LVDS_25 [get_ports {adc_d_*}] set_property IOSTANDARD LVDS_25 [get_ports {adc_d_*}]
......
components/solid/addr_table/sc_trig.xml
View file @ 0ee470e5
...@@ -2,6 +2,8 @@ ...@@ -2,6 +2,8 @@
<node id="csr" address="0x0" description="ctrl/stat reg" fwinfo="endpoint;width=2"> <node id="csr" address="0x0" description="ctrl/stat reg" fwinfo="endpoint;width=2">
<node id="ctrl" address="0x0"> <node id="ctrl" address="0x0">
<node id="dtmon_en" mask="0x1"/> <node id="dtmon_en" mask="0x1"/>
<node id="trig_in_en" mask="0x2"/>
<node id="trig_out_force" mask="0x4"/>
</node> </node>
<node id="evt_ctr" address="0x2"/> <node id="evt_ctr" address="0x2"/>
<node id="stat" address="0x3"> <node id="stat" address="0x3">
......
components/solid/firmware/hdl/sc_daq.vhd
View file @ 0ee470e5
...@@ -24,7 +24,6 @@ entity sc_daq is ...@@ -24,7 +24,6 @@ entity sc_daq is
clk_in_n: in std_logic; clk_in_n: in std_logic;
clk40: out std_logic; clk40: out std_logic;
sync_in: in std_logic; sync_in: in std_logic;
sync_out: out std_logic;
trig_in: in std_logic; trig_in: in std_logic;
trig_out: out std_logic; trig_out: out std_logic;
chan: in std_logic_vector(7 downto 0); chan: in std_logic_vector(7 downto 0);
...@@ -92,8 +91,7 @@ begin ...@@ -92,8 +91,7 @@ begin
clk160 => clk160, clk160 => clk160,
clk280 => clk280, clk280 => clk280,
sync_in => sync_in, sync_in => sync_in,
sync_out => sync_out, trig_in => trig_in,
ext_trig_in => trig_in,
sctr => sctr, sctr => sctr,
chan_sync_ctrl => sync_ctrl, chan_sync_ctrl => sync_ctrl,
trig_en => trig_en, trig_en => trig_en,
...@@ -119,7 +117,7 @@ begin ...@@ -119,7 +117,7 @@ begin
fake => fake fake => fake
); );
-- External / random trigger generator -- Random trigger generator
rtrig: entity work.sc_rtrig rtrig: entity work.sc_rtrig
port map( port map(
...@@ -131,10 +129,7 @@ begin ...@@ -131,10 +129,7 @@ begin
rst40 => rst40_i, rst40 => rst40_i,
rand => rand, rand => rand,
sctr => sctr, sctr => sctr,
force => force_trig, force => force_trig
hit => thresh_hit,
trig_in => trig_in,
trig_out => trig_out
); );
-- Data channels -- Data channels
...@@ -192,7 +187,8 @@ begin ...@@ -192,7 +187,8 @@ begin
zs_sel => zs_sel, zs_sel => zs_sel,
trig => chan_trig, trig => chan_trig,
force => force_trig, force => force_trig,
thresh_hit => thresh_hit, ext_trig_in => trig_in,
ext_trig_out => trig_out,
ro_d => trig_d, ro_d => trig_d,
ro_blkend => trig_blkend, ro_blkend => trig_blkend,
ro_we => trig_we, ro_we => trig_we,
......
components/solid/firmware/hdl/sc_local_trig.vhd
View file @ 0ee470e5
...@@ -28,7 +28,7 @@ entity sc_local_trig is ...@@ -28,7 +28,7 @@ entity sc_local_trig is
trig_valid: out std_logic; trig_valid: out std_logic;
trig_ack: in std_logic; trig_ack: in std_logic;
force: in std_logic; force: in std_logic;
thresh_hit: out std_logic; ext_trig_in: in std_logic;
ro_q: out std_logic_vector(31 downto 0); ro_q: out std_logic_vector(31 downto 0);
ro_valid: out std_logic; ro_valid: out std_logic;
ro_blkend: out std_logic; ro_blkend: out std_logic;
...@@ -64,7 +64,6 @@ begin ...@@ -64,7 +64,6 @@ begin
en => en, en => en,
mark => mark, mark => mark,
chan_trig => chan_trig, chan_trig => chan_trig,
hit => thresh_hit,
chan_act => cact(0), chan_act => cact(0),
valid => tv(0), valid => tv(0),
ack => ta(0) ack => ta(0)
......
components/solid/firmware/hdl/sc_rtrig.vhd
View file @ 0ee470e5
...@@ -19,10 +19,7 @@ entity sc_rtrig is ...@@ -19,10 +19,7 @@ entity sc_rtrig is
rst40: in std_logic; rst40: in std_logic;
rand: in std_logic_vector(31 downto 0); rand: in std_logic_vector(31 downto 0);
sctr: in std_logic_vector(47 downto 0); sctr: in std_logic_vector(47 downto 0);
force: out std_logic; force: out std_logic
hit: in std_logic;
trig_in: in std_logic;
trig_out: out std_logic
); );
end sc_rtrig; end sc_rtrig;
...@@ -33,6 +30,5 @@ begin ...@@ -33,6 +30,5 @@ begin
ipb_out <= IPB_RBUS_NULL; ipb_out <= IPB_RBUS_NULL;
force <= '0'; force <= '0';
trig_out <= '0';
end rtl; end rtl;
components/solid/firmware/hdl/sc_timing.vhd
View file @ 0ee470e5
...@@ -29,8 +29,7 @@ entity sc_timing is ...@@ -29,8 +29,7 @@ entity sc_timing is
clk160: out std_logic; -- chip 160MHz clock clk160: out std_logic; -- chip 160MHz clock
clk280: out std_logic; -- chip 280MHz clock clk280: out std_logic; -- chip 280MHz clock
sync_in: in std_logic; -- external sync signal in sync_in: in std_logic; -- external sync signal in
sync_out: out std_logic; -- external sync signal out trig_in: in std_logic; -- external trigger in
ext_trig_in: in std_logic;
sctr: out std_logic_vector(47 downto 0); -- sample counter sctr: out std_logic_vector(47 downto 0); -- sample counter
chan_sync_ctrl: out std_logic_vector(3 downto 0); -- Timing signals to channels chan_sync_ctrl: out std_logic_vector(3 downto 0); -- Timing signals to channels
trig_en: out std_logic; trig_en: out std_logic;
...@@ -51,8 +50,8 @@ architecture rtl of sc_timing is ...@@ -51,8 +50,8 @@ architecture rtl of sc_timing is
signal rst_ctr: unsigned(3 downto 0); signal rst_ctr: unsigned(3 downto 0);
signal ctrl_rst_ctr, ctrl_cap_ctr, ctrl_en_sync, ctrl_force_sync, ctrl_pipeline_en, ctrl_send_sync: std_logic; signal ctrl_rst_ctr, ctrl_cap_ctr, ctrl_en_sync, ctrl_force_sync, ctrl_pipeline_en, ctrl_send_sync: std_logic;
signal ctrl_chan_slip, ctrl_chan_rst_buf, ctrl_chan_cap, ctrl_chan_inc: std_logic; signal ctrl_chan_slip, ctrl_chan_rst_buf, ctrl_chan_cap, ctrl_chan_inc: std_logic;
signal frst, sync, wait_sync, sync_err, io_err: std_logic; signal frst, sync, sync_f, wait_sync, sync_err, io_err: std_logic;
signal sync_in_r, trig_in_r: std_logic; signal sync_in_r, trig_in_r, trig_in_r_d: std_logic;
signal sync_ctr, trig_ctr: unsigned(31 downto 0); signal sync_ctr, trig_ctr: unsigned(31 downto 0);
begin begin
...@@ -113,9 +112,33 @@ begin ...@@ -113,9 +112,33 @@ begin
stat(3) <= std_logic_vector(sync_ctr); stat(3) <= std_logic_vector(sync_ctr);
stat(4) <= std_logic_vector(trig_ctr); stat(4) <= std_logic_vector(trig_ctr);
-- Sync signals (need external sync here soon) -- External timing signals
sync <= ctrl_force_sync and stb(0) and wait_sync; sync_in_r <= sync_in when rising_edge(clk40_i); -- Should be IOB reg
trig_in_r <= trig_in when rising_edge(clk40_i); -- Should be IOB reg
trig_in_r_d <= trig_in_r when rising_dege(clk40_i);
process(clk40_i)
begin
if rising_edge(clk40_i) then
if rst40_i = '1' then
sync_ctr <= (others => '0');
trig_ctr <= (others => '0');
else
if sync_in_r = '1' then
sync_ctr <= sync_ctr + 1;
end if;
if trig_in_r = '1' and trig_in_r_d = '0' then
trig_ctr <= trig_ctr + 1;
end if;
end if;
end if;
end process;
-- Sync signals
sync <= (sync_in_r and ctrl_en_sync) or (ctrl_force_sync and stb(0));
sync_f <= sync and wait_sync;
process(clk40_i) process(clk40_i)
begin begin
...@@ -141,7 +164,7 @@ begin ...@@ -141,7 +164,7 @@ begin
process(clk40_i) process(clk40_i)
begin begin
if rising_edge(clk40_i) then if rising_edge(clk40_i) then
if rst40_i = '1' or sync = '1' then if rst40_i = '1' or sync_f = '1' then
sctr_i <= (others => '0'); sctr_i <= (others => '0');
else else
sctr_i <= sctr_i + 1; sctr_i <= sctr_i + 1;
...@@ -170,7 +193,7 @@ begin ...@@ -170,7 +193,7 @@ begin
clk40 => clk40_i, clk40 => clk40_i,
rst40 => rst40_i, rst40 => rst40_i,
en => ctrl_pipeline_en, en => ctrl_pipeline_en,
sync => sync, sync => sync_f,
sctr => sctr_i, sctr => sctr_i,
nzs_en => nzs_en, nzs_en => nzs_en,
zs_en => zs_en, zs_en => zs_en,
...@@ -197,27 +220,4 @@ begin ...@@ -197,27 +220,4 @@ begin
chan_sync_ctrl(2) <= ctrl_chan_cap and stb(0); -- cap start chan_sync_ctrl(2) <= ctrl_chan_cap and stb(0); -- cap start
chan_sync_ctrl(3) <= ctrl_chan_inc and stb(0); -- cap start chan_sync_ctrl(3) <= ctrl_chan_inc and stb(0); -- cap start
-- External timing interface
sync_out <= ctrl_send_sync and stb(0) when falling_edge(clk40_i);
sync_in_r <= sync_in when rising_edge(clk40_i);
trig_in_r <= ext_trig_in when rising_edge(clk40_i);
process(clk40_i)
begin
if rising_edge(clk40_i) then
if rst40_i = '1' then
sync_ctr <= (others => '0');
trig_ctr <= (others => '0');
else
if sync_in_r = '1' then
sync_ctr <= sync_ctr + 1;
end if;
if trig_in_r = '1' then
trig_ctr <= trig_ctr + 1;
end if;
end if;
end if;
end process;
end rtl; end rtl;
components/solid/firmware/hdl/sc_trig.vhd
View file @ 0ee470e5
...@@ -34,7 +34,8 @@ entity sc_trig is ...@@ -34,7 +34,8 @@ entity sc_trig is
zs_sel: out std_logic_vector(1 downto 0); zs_sel: out std_logic_vector(1 downto 0);
trig: in sc_trig_array; trig: in sc_trig_array;
force: in std_logic; force: in std_logic;
thresh_hit: out std_logic; ext_trig_in: in std_logic;
ext_trig_out: out std_logic;
ro_d: out std_logic_vector(31 downto 0); ro_d: out std_logic_vector(31 downto 0);
ro_blkend: out std_logic; ro_blkend: out std_logic;
ro_we: out std_logic; ro_we: out std_logic;
...@@ -54,7 +55,8 @@ architecture rtl of sc_trig is ...@@ -54,7 +55,8 @@ architecture rtl of sc_trig is
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0); signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal ctrl: ipb_reg_v(0 downto 0); signal ctrl: ipb_reg_v(0 downto 0);
signal stat: ipb_reg_v(1 downto 0); signal stat: ipb_reg_v(1 downto 0);
signal ctrl_dtmon_en: std_logic; signal stb: std_logic_vector(0 downto 0);
signal ctrl_dtmon_en, ctrl_trig_in_en, ctrl_trig_out_force: std_logic;
signal masks: ipb_reg_v(N_CHAN_TRG * 2 - 1 downto 0); signal masks: ipb_reg_v(N_CHAN_TRG * 2 - 1 downto 0);
signal trig_mask: std_logic_vector(N_TRG - 1 downto 0); signal trig_mask: std_logic_vector(N_TRG - 1 downto 0);
signal ctrig: sc_trig_array; signal ctrig: sc_trig_array;
...@@ -98,10 +100,13 @@ begin ...@@ -98,10 +100,13 @@ begin
ipb_out => ipbr(N_SLV_CSR), ipb_out => ipbr(N_SLV_CSR),
slv_clk => clk40, slv_clk => clk40,
d => stat, d => stat,
q => ctrl q => ctrl,
stb => stb
); );
ctrl_dtmon_en <= ctrl(0)(0); ctrl_dtmon_en <= ctrl(0)(0);
ctrl_trig_in_en <= ctrl(0)(1);
ctrl_trig_out_force <= ctrl(0)(2) and stb(0);
stat(0) <= X"0" & tctr; stat(0) <= X"0" & tctr;
stat(1) <= X"0000000" & "00" & rveto & err; stat(1) <= X"0000000" & "00" & rveto & err;
...@@ -171,7 +176,7 @@ begin ...@@ -171,7 +176,7 @@ begin
trig_valid => lvalid, trig_valid => lvalid,
trig_ack => lack, trig_ack => lack,
force => force, force => force,
thresh_hit => thresh_hit, ext_trig_in => ext_trig_in,
ro_q => t_q, ro_q => t_q,
ro_valid => t_valid, ro_valid => t_valid,
ro_blkend => t_blkend, ro_blkend => t_blkend,
...@@ -306,5 +311,10 @@ begin ...@@ -306,5 +311,10 @@ begin
keep => keep_i, keep => keep_i,
veto => veto_i veto => veto_i
); );
-- Ext trigger
trig_in <= ext_trig_in when rising_edge(clk40); -- Should be IOB reg
ext_trig_out <= trig_out or ctrl_trig_out_force when falling_edge(clk40); -- Should be IOB reg
end rtl; end rtl;
projects/64ch/firmware/hdl/payload.vhd
View file @ 0ee470e5
...@@ -40,9 +40,9 @@ entity payload is ...@@ -40,9 +40,9 @@ entity payload is
clkgen_rstn: out std_logic; clkgen_rstn: out std_logic;
clk_p: in std_logic; clk_p: in std_logic;
clk_n: in std_logic; clk_n: in std_logic;
t_sync: in std_logic; sync_in: in std_logic;
t_trig: in std_logic; trig_in: in std_logic;
t_busy: out std_logic; trig_out: out std_logic;
adc_d_p: in std_logic_vector(63 downto 0); adc_d_p: in std_logic_vector(63 downto 0);
adc_d_n: in std_logic_vector(63 downto 0) adc_d_n: in std_logic_vector(63 downto 0)
); );
...@@ -146,9 +146,9 @@ begin ...@@ -146,9 +146,9 @@ begin
clk_in_p => clk_p, clk_in_p => clk_p,
clk_in_n => clk_n, clk_in_n => clk_n,
clk40 => clk40, clk40 => clk40,
sync_in => t_sync, sync_in => sync_in,
sync_out => t_busy, trig_in => trig_in,
trig_in => t_trig, trig_out => trig_out,
chan => ctrl_chan, chan => ctrl_chan,
chan_err => chan_err, chan_err => chan_err,
d_p => adc_d_p, d_p => adc_d_p,
......
projects/8ch/firmware/hdl/payload.vhd
View file @ 0ee470e5
...@@ -50,10 +50,12 @@ entity payload is ...@@ -50,10 +50,12 @@ entity payload is
analog_scl: out std_logic; analog_scl: out std_logic;
analog_sda_i: in std_logic; analog_sda_i: in std_logic;
analog_sda_o: out std_logic; analog_sda_o: out std_logic;
sync_a_p: inout std_logic; sync_in_p: in std_logic;
sync_a_n: inout std_logic; sync_in_n: in std_logic;
sync_b_p: inout std_logic; trig_in_p: in std_logic;
sync_b_n: inout std_logic; trig_in_n: in std_logic;
trig_out_p: out std_logic;
trig_out_n: out std_logic;
clk_pll_p: out std_logic; clk_pll_p: out std_logic;
clk_pll_n: out std_logic clk_pll_n: out std_logic
); );
...@@ -67,7 +69,7 @@ architecture rtl of payload is ...@@ -67,7 +69,7 @@ architecture rtl of payload is
signal ctrl: ipb_reg_v(0 downto 0); signal ctrl: ipb_reg_v(0 downto 0);
signal stat: ipb_reg_v(1 downto 0); signal stat: ipb_reg_v(1 downto 0);
signal clk40: std_logic; signal clk40: std_logic;
signal sync_in, sync_out: std_logic; signal sync_in, trig_in, trig_out: std_logic;
signal ctrl_rst_mmcm, locked, idelayctrl_rdy, ctrl_rst_idelayctrl, ctrl_sync_mode: std_logic; signal ctrl_rst_mmcm, locked, idelayctrl_rdy, ctrl_rst_idelayctrl, ctrl_sync_mode: std_logic;
signal ctrl_chan: std_logic_vector(7 downto 0); signal ctrl_chan: std_logic_vector(7 downto 0);
signal ctrl_board_id: std_logic_vector(7 downto 0); signal ctrl_board_id: std_logic_vector(7 downto 0);
...@@ -157,7 +159,37 @@ begin ...@@ -157,7 +159,37 @@ begin
analog_sda_o => analog_sda_o, analog_sda_o => analog_sda_o,
analog_sda_i => analog_sda_i analog_sda_i => analog_sda_i
); );
-- iobufs
ibuf_sync_in: IBUFDS
port map(
i => sync_in_p,
ib => sync_in_n,
o => sync_in
);
ibuf_trig_in: IBUFDS
port map(
i => trig_in_p,
ib => trig_in_n,
o => trig_in
);
obuf_trig_out: OBUFDS
port map(
i => trig_out,
o => trig_out_p,
ob => trig_out_n
);
obuf_clk_pll: OBUFDS
port map(
i => '0',
o => clk_pll_p,
ob => clk_pll_n
);
-- DAQ core -- DAQ core
daq: entity work.sc_daq daq: entity work.sc_daq
...@@ -172,8 +204,8 @@ begin ...@@ -172,8 +204,8 @@ begin
clk_in_n => clk40_n, clk_in_n => clk40_n,
clk40 => clk40, clk40 => clk40,
sync_in => sync_in, sync_in => sync_in,
sync_out => sync_out, trig_in => trig_in,
trig_in => '0', trig_out => trig_out,
chan => ctrl_chan, chan => ctrl_chan,
chan_err => chan_err, chan_err => chan_err,
d_p => adc_d_p, d_p => adc_d_p,
...@@ -182,21 +214,5 @@ begin ...@@ -182,21 +214,5 @@ begin
rst125 => rst125, rst125 => rst125,
board_id => ctrl_board_id board_id => ctrl_board_id
); );
-- Clocks n stuff
switch: entity work.sync_routing
port map(
clk40 => clk40,
ctrl => ctrl_sync_mode,
sync_out => sync_out,
sync_in => sync_in,
sync_a_p => sync_a_p,
sync_a_n => sync_a_n,
sync_b_p => sync_b_p,
sync_b_n => sync_b_n,
clk_pll_p => clk_pll_p,
clk_pll_n => clk_pll_n
);
end rtl; end rtl;
projects/timing/addr_table/top.xml
View file @ 0ee470e5
<node id="TOP"> <node id="TOP">
<node id="csr" address="0x0" fwinfo="endpoint;width=1"> <node id="csr" address="0x0" fwinfo="endpoint;width=0">
<node id="ctrl" address="0x0"> <node id="ctrl" address="0x0">
<node id="soft_rst" mask="0x1"/> <node id="soft_rst" mask="0x1"/>
<node id="nuke" mask="0x2"/> <node id="nuke" mask="0x2"/>
<node id="rst_mmcm" mask="0x4"/> <node id="pll_rst" mask="0x4"/>
<node id="trig" mask="0x8"/> <node id="rst" mask="0x8"/)
<node id="sync" mask="0x10"/> <node id="layer" mask="0x10"/>
<node id="trig_sel" mask="0x20"/> <node id="trig_in_mask" mask="0x3ff00"/>
<node id="sync_sel" mask="0x40"/>
<node id="busy" mask="0x80"/>
</node>
<node id="stat" address="0x1">
<node id="mmcm_locked" mask="0x1"/>
</node> </node>
</node> </node>
<node id="sync_ctrl" address="0x2" fwinfo="endpoint;width=0"/>
<node id="en_sync" mask="0x1"/>
<node id="en_trig_out" mask="0x2"/>
<node id="force_trig_out" mask="0x4"/>
</node>
<node id="i2c" address="0x8" module="file://opencores_i2c.xml"/> <node id="i2c" address="0x8" module="file://opencores_i2c.xml"/>
<node id="freq_ctr" address="0x10" module="file://freq_ctr.xml"/> <node id="freq_ctr" address="0x10" module="file://freq_ctr.xml"/>
</node> </node>
projects/timing/firmware/hdl/payload.vhd
View file @ 0ee470e5
...@@ -3,6 +3,7 @@ ...@@ -3,6 +3,7 @@
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.ipbus.all; use work.ipbus.all;
use work.ipbus_decode_top.all; use work.ipbus_decode_top.all;
...@@ -51,15 +52,19 @@ end payload; ...@@ -51,15 +52,19 @@ end payload;
architecture rtl of payload is architecture rtl of payload is
constant BLK_RADIX: integer := 8; -- 256 sample blocks
signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0); signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0); signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal ctrl, stat: ipb_reg_v(0 downto 0); signal ctrl, sync_ctrl: ipb_reg_v(0 downto 0);
signal stb: std_logic_vector(0 downto 0);
signal scl, sda_i, sda_o: std_logic; signal scl, sda_i, sda_o: std_logic;
signal ctrl_trig, ctrl_sync, ctrl_trig_sel, ctrl_sync_sel, ctrl_busy: std_logic; signal ctrl_layer, ctrl_pll_rstn, ctrl_rst, ctrl_en_sync, ctrl_en_trig_out, ctrl_force_trig_out: std_logic;
signal ctrl_trig_in_mask: std_logic_vector(9 downto 0);
signal clki, clkdiv: std_logic; signal clki, clkdiv: std_logic;
signal sync_sel, trig_sel, sync_in_us, sync_out_ds, trig_in_us, trig_out_ds, trig_out_us: std_logic;
-- attribute IOB: string; signal trig_in_ds, trig_i: std_logic_vector(9 downto 0);
-- attribute IOB of sfp_dout: signal is "TRUE"; signal ctr: unsigned(BLK_RADIX - 1 downto 0);
begin begin
...@@ -83,26 +88,44 @@ begin ...@@ -83,26 +88,44 @@ begin
csr: entity work.ipbus_ctrlreg_v csr: entity work.ipbus_ctrlreg_v
generic map( generic map(
N_CTRL => 1, N_CTRL => 1,
N_STAT => 5 N_STAT => 0
) )
port map( port map(
clk => ipb_clk, clk => ipb_clk,
reset => ipb_rst, reset => ipb_rst,
ipbus_in => ipbw(N_SLV_CSR), ipbus_in => ipbw(N_SLV_CSR),
ipbus_out => ipbr(N_SLV_CSR), ipbus_out => ipbr(N_SLV_CSR),
d => stat,
q => ctrl q => ctrl
); );
soft_rst <= ctrl(0)(0); soft_rst <= ctrl(0)(0);
nuke <= ctrl(0)(1); nuke <= ctrl(0)(1);
rst <= ctrl(0)(2); ctrl_pll_rstn <= not ctrl(0)(2);
ctrl_trig <= ctrl(0)(3); ctrl_rst <= ctrl(0)(3);
ctrl_sync <= ctrl(0)(4); ctrl_layer <= ctrl(0)(4);
ctrl_trig_sel <= ctrl(0)(5); ctrl_trig_in_mask <= ctrl(0)(17 downto 8);
ctrl_sync_sel <= ctrl(0)(6);
ctrl_busy <= ctrl(0)(7); -- Sync ctrl
sync_csr: entity work.ipbus_syncreg_v
generic map(
N_CTRL => 1,
N_STAT => 0
)
port map(
clk => ipb_clk,
rst => ipb_rst,
ipb_in => ipbw(N_SLV_SYNC_CTRL),
ipb_out => ipbr(N_SLV_SYNC_CTRL),
slv_clk => clki,
q => sync_ctrl,
stb => stb
);
ctrl_en_sync <= sync_ctrl(0)(0);
ctrl_en_trig_out <= sync_ctrl(0)(1);
ctrl_force_trig_out <= sync_ctrl(0)(2) and stb(0);
-- General IO -- General IO
userled <= '0'; userled <= '0';
...@@ -119,12 +142,32 @@ begin ...@@ -119,12 +142,32 @@ begin
sda_o => sda_o, sda_o => sda_o,
sda_i => sda_i sda_i => sda_i
); );
-- The business
process(clki)
begin
if rising_edge(clki) then
if ctrl_en_sync = '1' then
ctr <= (others => '0');
else
ctr <= ctr + 1;
end if;
end if;
end process;
sync_sel <= not ctrl_layer; -- From FPGA for layer 0, from upstream input for layer 1
trig_sel <= not ctrl_layer; -- From FPGA for layer 0, from upstream input for layer 1
sync_out_ds <= ctrl_en_sync and not or_reduce(std_logic_vector(ctr)) when falling_edge(clki); -- Sync out downstream
trig_i <= trig_in_ds when rising_edge(clki); -- Should be IOB reg
trig_out_ds <= or_reduce(trig_i and ctrl_trig_in_mask) and ctrl_en_trig_out when falling_edge(clki); -- Trig out downstream
trig_out_us <= or_reduce(trig_i and ctrl_trig_in_mask) when falling_edge(clki); -- Trig out upstream
-- Cable IO -- Cable IO
bufs: entity work.sc_timing_iobufs bufs: entity work.sc_timing_iobufs
port map( port map(
clk_rstn => '1', clk_rstn => ctrl_clk_rstn,
clk_rstn_p => clk_rstn_p, clk_rstn_p => clk_rstn_p,
clk_rstn_n => clk_rstn_n, clk_rstn_n => clk_rstn_n,
clk => '0', clk => '0',
...@@ -133,22 +176,22 @@ begin ...@@ -133,22 +176,22 @@ begin
clk_i => clki, clk_i => clki,
clk_i_p => clk_i_p, clk_i_p => clk_i_p,
clk_i_n => clk_i_n, clk_i_n => clk_i_n,
trig_o => ctrl_trig_o, trig_o => trig_out_ds,
trig_o_p => trig_o_p, trig_o_p => trig_o_p,
trig_o_n => trig_o_n, trig_o_n => trig_o_n,
trig_i => open, trig_i => trig_in_us,
trig_i_p => trig_i_p, trig_i_p => trig_i_p,
trig_i_n => trig_i_n, trig_i_n => trig_i_n,
sync_o => ctrl_sync_o, sync_o => sync_out_ds,
sync_o_p => sync_o_p, sync_o_p => sync_o_p,
sync_o_n => sync_o_n, sync_o_n => sync_o_n,
sync_i => open, sync_i => sync_in_us,
sync_i_p => sync_i_p, sync_i_p => sync_i_p,
sync_i_n => sync_i_n, sync_i_n => sync_i_n,
trig_sel => ctrl_trig_sel, trig_sel => trig_sel,
trig_sel_p => trig_sel_p, trig_sel_p => trig_sel_p,
trig_sel_n => trig_sel_n, trig_sel_n => trig_sel_n,
sync_sel => ctrl_sync_sel, sync_sel => sync_sel,
sync_sel_p => sync_sel_p, sync_sel_p => sync_sel_p,
sync_sel_n => sync_sel_n, sync_sel_n => sync_sel_n,
scl => scl, scl => scl,
...@@ -160,10 +203,10 @@ begin ...@@ -160,10 +203,10 @@ begin
sda_i => sda_i, sda_i => sda_i,
sda_i_p => sda_i_p, sda_i_p => sda_i_p,
sda_i_n => sda_i_n, sda_i_n => sda_i_n,
busy_o => ctrl_busy_o, busy_o => trig_out_us,
busy_o_p => busy_o_p, busy_o_p => busy_o_p,
busy_o_n => busy_o_n, busy_o_n => busy_o_n,
busy_i => open, busy_i => trig_in_ds,
busy_i_p => busy_i_p, busy_i_p => busy_i_p,
busy_i_n => busy_i_n busy_i_n => busy_i_n
); );
......
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