Skip to content

E
euro-adc-65m-14b-40cha-gw
Commit 0be6a6be authored by David Cussans's avatar David Cussans
Browse files
Options

Hacking DMN's code to add trigger and sync counters 

( and firmware register)
parent e8ff4c06
Hide whitespace changes
Inline Side-by-side
Showing with 105 additions and 37 deletions
projects/timing/addr_table/top.xml
View file @ 0be6a6be
<node id="TOP">
<node id="csr" address="0x0" fwinfo="endpoint;width=0">
<node id="csr" address="0x0" fwinfo="endpoint;width=3">
<node id="ctrl" address="0x0">
<node id="soft_rst" mask="0x1"/>
<node id="nuke" mask="0x2"/>
<node id="pll_rst" mask="0x4"/>
<node id="rst" mask="0x8"/>
<node id="layer" mask="0x10"/>
<node id="trig_in_mask" mask="0x3ff00"/>
<node id="trig_in_mask" mask="0xffc0"/>
</node>
<node id="id" address="0x4"/>
<node id="sync_out_ctr" address="0x5"/>
<node id="trig_out_ctr" address="0x6"/>
<node id="trig_in_ctr" address="0x7"/>
</node>
<node id="sync_ctrl" address="0x2" fwinfo="endpoint;width=0">
<node id="sync_ctrl" address="0x8" fwinfo="endpoint;width=0">
<node id="en_sync" mask="0x1"/>
<node id="en_trig_out" mask="0x2"/>
<node id="force_trig_out" mask="0x4"/>
<node id="rst_counters" mask="0x8"/>
</node>
<node id="i2c" address="0x8" module="file://opencores_i2c.xml"/>
<node id="freq_ctr" address="0x10" module="file://freq_ctr.xml"/>
<node id="i2c" address="0x10" module="file://opencores_i2c.xml"/>
<node id="freq_ctr" address="0x20" module="file://freq_ctr.xml"/>
</node>
projects/timing/firmware/hdl/ipbus_decode_top.vhd
View file @ 0be6a6be
......@@ -17,7 +17,7 @@ package ipbus_decode_top is
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_top(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-- START automatically generated VHDL the Fri Jul 14 11:59:48 2017
-- START automatically generated VHDL the Thu Sep 7 13:10:04 2017
constant N_SLV_CSR: integer := 0;
constant N_SLV_SYNC_CTRL: integer := 1;
constant N_SLV_I2C: integer := 2;
......@@ -34,15 +34,15 @@ package body ipbus_decode_top is
variable sel: ipbus_sel_t;
begin
-- START automatically generated VHDL the Fri Jul 14 11:59:48 2017
if std_match(addr, "---------------------------00-0-") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x0000001a
elsif std_match(addr, "---------------------------00-1-") then
sel := ipbus_sel_t(to_unsigned(N_SLV_SYNC_CTRL, IPBUS_SEL_WIDTH)); -- sync_ctrl / base 0x00000002 / mask 0x0000001a
elsif std_match(addr, "---------------------------01---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_I2C, IPBUS_SEL_WIDTH)); -- i2c / base 0x00000008 / mask 0x00000018
elsif std_match(addr, "---------------------------10-0-") then
sel := ipbus_sel_t(to_unsigned(N_SLV_FREQ_CTR, IPBUS_SEL_WIDTH)); -- freq_ctr / base 0x00000010 / mask 0x0000001a
-- START automatically generated VHDL the Thu Sep 7 13:10:04 2017
if std_match(addr, "--------------------------000---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x00000038
elsif std_match(addr, "--------------------------001---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_SYNC_CTRL, IPBUS_SEL_WIDTH)); -- sync_ctrl / base 0x00000008 / mask 0x00000038
elsif std_match(addr, "--------------------------010---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_I2C, IPBUS_SEL_WIDTH)); -- i2c / base 0x00000010 / mask 0x00000038
elsif std_match(addr, "--------------------------100---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_FREQ_CTR, IPBUS_SEL_WIDTH)); -- freq_ctr / base 0x00000020 / mask 0x00000038
-- END automatically generated VHDL
else
......
projects/timing/firmware/hdl/payload.vhd
View file @ 0be6a6be
......@@ -10,7 +10,10 @@ use work.ipbus_decode_top.all;
use work.ipbus_reg_types.all;
entity payload is
port(
generic (
FW_REV : std_logic_vector(15 downto 0) := X"0004"
);
port(
ipb_clk: in std_logic;
ipb_rst: in std_logic;
ipb_in: in ipb_wbus;
......@@ -45,8 +48,8 @@ entity payload is
sda_i_n: in std_logic;
busy_o_p: out std_logic;
busy_o_n: out std_logic;
busy_i_p: in std_logic_vector(7 downto 0);
busy_i_n: in std_logic_vector(7 downto 0)
busy_i_p: in std_logic_vector(9 downto 0);
busy_i_n: in std_logic_vector(9 downto 0)
);
end payload;
......@@ -58,17 +61,31 @@ architecture rtl of payload is
signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal ctrl, sync_ctrl: ipb_reg_v(0 downto 0);
signal stat: ipb_reg_v(3 downto 0);
signal stb: std_logic_vector(0 downto 0);
signal scl, sda_i, sda_o: std_logic;
signal ctrl_layer, ctrl_pll_rstn, ctrl_rst, ctrl_en_sync, ctrl_en_trig_out, ctrl_force_trig_out: std_logic;
signal ctrl_trig_in_mask: std_logic_vector(7 downto 0);
signal ctrl_trig_in_mask: std_logic_vector(9 downto 0) := (others => '0');
signal clki: std_logic;
signal clkdiv: std_logic_vector(0 downto 0);
signal sync_sel, trig_sel, sync_in_us, sync_out_ds, trig_in_us, trig_out_ds, trig_out_us: std_logic;
signal trig_in_ds, trig_i: std_logic_vector(7 downto 0);
signal trig_in_ds, trig_i,trig_i_masked: std_logic_vector(9 downto 0);
signal trig_ir: std_logic;
signal ctr: unsigned(BLK_RADIX - 1 downto 0);
signal sync_out_ctr, trig_out_ctr , trig_in_ctr : unsigned(31 downto 0) := ( others => '0' );
signal trig_ir_d1 , trig_ir_d2 : std_logic := '0';
signal rst_counters : std_logic := '0';
-- mark signals for debugging
attribute mark_debug : string;
attribute mark_debug of trig_in_ds: signal is "true";
attribute mark_debug of trig_i_masked: signal is "true";
attribute mark_debug of trig_out_us: signal is "true";
attribute mark_debug of trig_out_ds: signal is "true";
attribute mark_debug of sync_in_us: signal is "true";
attribute mark_debug of sync_out_ds: signal is "true";
attribute mark_debug of ctrl_force_trig_out: signal is "true";
attribute mark_debug of ctrl_en_trig_out: signal is "true";
begin
-- ipbus address decode
......@@ -91,13 +108,14 @@ begin
csr: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => 1,
N_STAT => 0
N_STAT => 4
)
port map(
clk => ipb_clk,
reset => ipb_rst,
ipbus_in => ipbw(N_SLV_CSR),
ipbus_out => ipbr(N_SLV_CSR),
d => stat,
q => ctrl
);
......@@ -106,8 +124,44 @@ begin
ctrl_pll_rstn <= not ctrl(0)(2);
ctrl_rst <= ctrl(0)(3);
ctrl_layer <= ctrl(0)(4);
ctrl_trig_in_mask <= ctrl(0)(15 downto 8);
ctrl_trig_in_mask <= ctrl(0)(15 downto 6);
-- Status registers
stat(0) <= X"a753" & FW_REV;
stat(1) <= std_logic_vector(sync_out_ctr);
stat(2) <= std_logic_vector(trig_out_ctr);
stat(3) <= std_logic_vector(trig_in_ctr);
-- trigger and sync Counters
process(clki)
begin
if rising_edge(clki) then
if rst_counters = '1' then
sync_out_ctr <= (others => '0');
trig_out_ctr <= (others => '0');
trig_in_ctr <= (others => '0');
else
if sync_out_ds = '1' then
sync_out_ctr <= sync_out_ctr + 1;
end if;
if trig_out_ds = '1' then
trig_out_ctr <= trig_out_ctr + 1;
end if;
-- look for rising edge of incoming trigger
if trig_ir_d1 = '1' and trig_ir_d2 = '0' then
trig_in_ctr <= trig_in_ctr + 1;
end if;
end if;
trig_ir_d1 <= or_reduce(trig_i and ctrl_trig_in_mask);
trig_ir_d2 <= trig_ir_d1;
end if;
end process;
-- Sync ctrl
sync_csr: entity work.ipbus_syncreg_v
......@@ -128,6 +182,7 @@ begin
ctrl_en_sync <= sync_ctrl(0)(0);
ctrl_en_trig_out <= sync_ctrl(0)(1);
ctrl_force_trig_out <= sync_ctrl(0)(2) and stb(0);
rst_counters <= sync_ctrl(0)(3) and stb(0);
-- General IO
......@@ -159,11 +214,17 @@ begin
end if;
end process;
sync_sel <= not ctrl_layer; -- From FPGA for layer 0, from upstream input for layer 1
-- ctrl_layer =0 --> sync,trig are controlled by local FPGA.
-- ctrl_layer=1 --> sync,trig are conrolled from upstream HDMI
sync_sel <= not ctrl_layer; -- Set sync_sel=1 for output sync to be
-- driven by FPGA. Set sync_sel=0 to be
-- driven from upstream
-- (From FPGA for layer 0, from upstream input for layer 1)
trig_sel <= not ctrl_layer; -- From FPGA for layer 0, from upstream input for layer 1
sync_out_ds <= ctrl_en_sync and not or_reduce(std_logic_vector(ctr)) when falling_edge(clki); -- Sync out downstream
trig_i <= trig_in_ds when rising_edge(clki); -- Should be IOB reg
trig_ir <= (or_reduce(trig_i and ctrl_trig_in_mask) or ctrl_force_trig_out) and ctrl_en_trig_out;
trig_i_masked <= (trig_i and ctrl_trig_in_mask) when rising_edge(clki);
trig_ir <= ((or_reduce(trig_i_masked) or ctrl_force_trig_out) and ctrl_en_trig_out) when rising_edge(clki) ;
trig_out_ds <= trig_ir when falling_edge(clki); -- Trig out downstream
trig_out_us <= trig_ir when falling_edge(clki); -- Trig out upstream
......
projects/timing/firmware/hdl/sc_timing_iobufs.vhd
View file @ 0be6a6be
......@@ -51,9 +51,9 @@ entity sc_timing_iobufs is
busy_o: in std_logic;
busy_o_p: out std_logic;
busy_o_n: out std_logic;
busy_i: out std_logic_vector(7 downto 0);
busy_i_p: in std_logic_vector(7 downto 0);
busy_i_n: in std_logic_vector(7 downto 0)
busy_i: out std_logic_vector(9 downto 0);
busy_i_p: in std_logic_vector(9 downto 0);
busy_i_n: in std_logic_vector(9 downto 0)
);
end sc_timing_iobufs;
......@@ -175,7 +175,7 @@ begin
ob => busy_o_n
);
busy_i_gen: for i in 7 downto 0 generate
busy_i_gen: for i in 9 downto 0 generate
ibuf_sda_i: IBUFDS
port map(
......
projects/timing/firmware/hdl/top_enclustra_ax3_pm3.vhd
View file @ 0be6a6be
......@@ -15,7 +15,7 @@ use work.ipbus.ALL;
entity top is port(
sysclk: in std_logic;
leds: out std_logic_vector(3 downto 0); -- status LEDs
cfg: in std_logic_vector(3 downto 0); -- switches
-- cfg: in std_logic_vector(3 downto 0); -- switches
rgmii_txd: out std_logic_vector(3 downto 0);
rgmii_tx_ctl: out std_logic;
rgmii_txc: out std_logic;
......@@ -49,8 +49,8 @@ entity top is port(
sda_i_n: in std_logic;
busy_o_p: out std_logic;
busy_o_n: out std_logic;
busy_i_p: in std_logic_vector(7 downto 0);
busy_i_n: in std_logic_vector(7 downto 0)
busy_i_p: in std_logic_vector(9 downto 0);
busy_i_n: in std_logic_vector(9 downto 0)
);
end top;
......@@ -90,7 +90,7 @@ begin
ipb_out => ipb_out
);
leds <= not (or_reduce(cfg) & userled & inf_leds);
leds <= not ('0' & userled & inf_leds);
phy_rstn <= not phy_rst_e;
mac_addr <= X"020ddba1ebc7"; -- Careful here, arbitrary addresses do not always work
......
projects/timing/firmware/ucf/pc054_ax3_pm3.tcl
View file @ 0be6a6be
......@@ -49,8 +49,9 @@ set_property PACKAGE_PIN H6 [get_ports {busy_i_p[6]}]
set_property PACKAGE_PIN H5 [get_ports {busy_i_n[6]}]
set_property PACKAGE_PIN H1 [get_ports {busy_i_p[7]}]
set_property PACKAGE_PIN G1 [get_ports {busy_i_n[7]}]
#set_property PACKAGE_PIN K2 [get_ports {busy_i_p[8]}]
#set_property PACKAGE_PIN K1 [get_ports {busy_i_n[8]}]
#set_property PACKAGE_PIN C4 [get_ports {busy_i_p[9]}]
#set_property PACKAGE_PIN B4 [get_ports {busy_i_n[9]}]
# busy 8,9 clash with cfg[3..0] so make sure these ports are commented out in enclustra_ax3_pm3.tcl
set_property PACKAGE_PIN K2 [get_ports {busy_i_p[8]}]
set_property PACKAGE_PIN K1 [get_ports {busy_i_n[8]}]
set_property PACKAGE_PIN C4 [get_ports {busy_i_p[9]}]
set_property PACKAGE_PIN B4 [get_ports {busy_i_n[9]}]
false_path {clk_rstn_* clk_o_* clk_i_* trig_o_* trig_i_* sync_o_* sync_i_* trig_sel_* sync_sel_* scl_* sda_* busy_o_* busy_i_*} sysclk
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment