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euro-adc-65m-14b-40cha-gw
Commit 05a2633f authored by Dave Newbold's avatar Dave Newbold
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Adding random trigger block back in

parent 628590ca
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Showing with 46 additions and 5 deletions
components/solid/addr_table/sc_daq.xml
View file @ 05a2633f
......@@ -2,7 +2,7 @@
<node id="chan" address="0x0" module="file://sc_chan.xml"/>
<node id="timing" address="0x10" module="file://sc_timing.xml"/>
<node id="fake" address="0x20" module="file://sc_fake.xml"/>
<node id="rtrig" address="0x28" fwinfo="endpoint;width=0"/>
<node id="rtrig" address="0x28" fwinfo="file://sc_rtrig.xml"/>
<node id="tlink" address="0x30" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x40" module="file://sc_trig.xml"/>
<node id="roc" address="0x60" module="file://sc_roc.xml"/>
......
components/solid/addr_table/sc_rtrig.xml 0 → 100644
View file @ 05a2633f
<node id="rtrig" description="Random / external trigger generator" fwinfo="endpoint; width=0">
<node id="en" mask="0x1"/>
<node id="dist" mask="0x2"/>
<node id="div" mask="0x3f00"/>
</node>
components/solid/firmware/cfg/sc_daq.dep
View file @ 05a2633f
src sc_daq.vhd
src ipbus_decode_sc_daq.vhd
addrtab -t sc_daq.xml
src sc_rtrig.vhd
include sc_timing.dep sc_fake.dep sc_chan.dep sc_trig.dep sc_trig_link.dep sc_roc.dep
include sc_timing.dep sc_fake.dep sc_chan.dep sc_trig.dep sc_trig_link.dep sc_roc.dep sc_rtrig.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
components/solid/firmware/cfg/sc_rtrig.dep 0 → 100644
View file @ 05a2633f
src sc_rtrig.vhd
addrtab sc_rtrig.xml
src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_v.vhd
src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_types.vhd
components/solid/firmware/hdl/sc_rtrig.vhd
View file @ 05a2633f
......@@ -6,8 +6,12 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_misc.all;
use work.ipbus.all;
use work.ipbus_reg_types.all;
use work.top_decl.all;
entity sc_rtrig is
port(
......@@ -26,9 +30,37 @@ end sc_rtrig;
architecture rtl of sc_rtrig is
signal q: ipb_reg_v(0 downto 0);
signal ctrl_en, ctrl_mode: std_logic;
signal ctrl_div: std_logic_vector(5 downto 0);
signal mask: std_logic_vector(23 downto 0);
signal t: std_logic;
begin
ipb_out <= IPB_RBUS_NULL;
force <= '0';
mask: entity work.ipbus_reg_v
generic map(
N_REG => N_CHAN_TRG * 2
)
port map(
clk => clk,
reset => rst,
ipbus_in => ipb_in,
ipbus_out => ipb_out,
q => q
);
ctrl_en <= q(0)(0);
ctrl_mode <= q(0)(1);
ctrl_div <= q(0)(13 downto 8);
mgen: for i in mask'range generate
mask(i) <= '0' when i > to_integer(unsigned(ctrl_div)) else '1';
end generate;
t <= ((not ctrl_mode and not or_reduce(rand(mask'range) and mask)) or
(ctrl_mode and not or_reduce(sctr(BLK_RADIX + mask'left downto BLK_RADIX) and mask))) and ctrl_en;
force <= t;
end rtl;
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