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euro-adc-65m-14b-40cha-gw
Commit 044ae9e4 authored by Dave Newbold's avatar Dave Newbold
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Adding test output

parent a1124bf0
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Showing with 46 additions and 4 deletions
components/solid/addr_table/sc_chan.xml
View file @ 044ae9e4
......@@ -6,6 +6,7 @@
<node id="invert" mask="0x4"/>
<node id="mode" mask="0x10"/>
<node id="src" mask="0xc0"/>
<node id="tt" mask="0x100"/>
</node>
<node id="stat" address="0x1">
<node id="cap_full" mask="0x1"/>
......
components/solid/firmware/hdl/sc_chan.vhd
View file @ 044ae9e4
......@@ -74,6 +74,7 @@ architecture rtl of sc_chan is
signal sctr_p: std_logic_vector(11 downto 0);
signal dr_d: std_logic_vector(31 downto 0);
signal ro_en, keep_i, flush_i, err_i, req, blkend, dr_blkend, dr_wen: std_logic;
signal ctrl_tt: std_logic;
begin
......@@ -113,6 +114,7 @@ begin
ctrl_invert <= ctrl(0)(2);
ctrl_mode <= ctrl(0)(4);
ctrl_src <= ctrl(0)(7 downto 6);
ctrl_tt <= not ctrl(0)(8);
slip <= sync_ctrl(0) and ctrl_en_sync; -- CDC
cap <= sync_ctrl(1) and ctrl_en_sync; -- CDC
......@@ -145,7 +147,8 @@ begin
slip => slip,
inc => inc,
cntout => cntout,
q => d_in
q => d_in,
tt => ctrl_tt
);
d_in_i <= d_in when ctrl_invert = '0' else not d_in;
......
components/solid/firmware/hdl/sc_input_serdes.vhd
View file @ 044ae9e4
......@@ -6,6 +6,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library unisim;
use unisim.VComponents.all;
......@@ -15,12 +16,13 @@ entity sc_input_serdes is
clk: in std_logic;
rst: in std_logic;
clk_s: in std_logic;
d_p: in std_logic;
d_n: in std_logic;
d_p: inout std_logic;
d_n: inout std_logic;
slip: in std_logic;
inc: in std_logic;
cntout: out std_logic_vector(4 downto 0);
q: out std_logic_vector(13 downto 0)
q: out std_logic_vector(13 downto 0);
tt: in std_logic
);
end sc_input_serdes;
......@@ -31,6 +33,8 @@ architecture rtl of sc_input_serdes is
signal d: std_logic_vector(13 downto 0);
signal s1, s2: std_logic;
signal clk_sb: std_logic;
signal k: std_logic_vector(13 downto 0);
signal tq: std_logic;
begin
......@@ -135,5 +139,39 @@ begin
dynclkdivsel => '0',
dynclksel => '0'
);
-- Test logic
process(clk_s)
begin
if rising_edge(clk_s) then
if rst = '1' then
k <= "00000000000001";
else
k <= k(12 downto 0) & '0';
end if;
end if;
end process;
oreg: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE"
)
port map(
q => tq,
c => clk_s,
ce => '1',
d1 => k(0),
d2 => k(1),
s => '0'
);
obuf: OBUFTDS
port map(
i => tq,
t => tt,
o => d_p,
ob => d_n
);
end rtl;
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