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diot
diot-wic-gw
Commits
e882fc3d
Commit
e882fc3d
authored
Sep 03, 2018
by
Denia Bouhired-Ferrag
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adds general cores to manifest
parent
2c11f5cf
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2 changed files
with
5 additions
and
3 deletions
+5
-3
Manifest.py
hdl/testbench/diot_test/Manifest.py
+4
-3
wave.do
hdl/testbench/diot_test/wave.do
+1
-0
No files found.
hdl/testbench/diot_test/Manifest.py
View file @
e882fc3d
...
...
@@ -3,7 +3,7 @@ sim_tool = "modelsim"
top_module
=
"main"
vcom_opt
=
"-2008 -mixedsvvh l"
vlog_opt
=
"+incdir+../../ip_cores/masterfip-gw/testbench/top_mt"
vlog_opt
=
"+incdir+../../ip_cores/masterfip-gw/testbench/top_mt
+incdir+../../sim
"
# create a fake proasic3 library needed by nanofip
sim_pre_cmd
=
"vlib ../fake_proasic3; vmap proasic3 ../fake_proasic3"
...
...
@@ -13,7 +13,8 @@ include_dirs = [ "../../sim", "../../sim/include", "../../sim/include/wb" ]
modules
=
{
"local"
:
[
"../../rtl"
,
"../../top/spec_test"
,
"../../ip_cores/nanofip-gateware/top"
]}
"local"
:
[
"../../sim/fcm2"
,
"../../rtl"
,
"../../top/spec_test"
,
"../../ip_cores/nanofip-gateware/top"
,
"../../ip_cores/general-cores/"
]}
#, "../../ip_cores/masterfip-gw/testbench/top_mt"]}
hdl/testbench/diot_test/wave.do
View file @
e882fc3d
...
...
@@ -27,6 +27,7 @@ add wave -noupdate -expand -group WIC_MAIN /tb_top/harness/DUT/cmp_wic_main/var1
add wave -noupdate -expand -group WIC_MAIN /tb_top/harness/DUT/cmp_wic_main/var1_reg
add wave -noupdate /tb_top/harness/DUT_nf_if/send_data
add wave -noupdate /tb_top/harness/DUT_nf_if/input_data
add wave -position 21 sim:/tb_top/harness/DUT/cmp_wic_main/var3_reg
add wave -noupdate -expand -group WIC_MAIN /tb_top/harness/DUT/cmp_wic_main/state
add wave -noupdate -expand -group WIC_MAIN /tb_top/harness/DUT/cmp_wic_main/update_out
add wave -noupdate -expand -group WIC_MAIN /tb_top/harness/DUT/cmp_wic_main/bckpl_relays_o
...
...
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