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diot-wic-gw
Commit c4b3209c authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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WIP: Testbench runs, but with little bug on read transactions. No monitoring or checking performed

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hdl/testbench/diot_test/DIOT_pkg.sv
View file @ c4b3209c
......@@ -6,8 +6,7 @@
package DIOT_pkg;
`include "bases.sv"
`include "tb_classes.sv"
`include "wic_classes.sv"
endpackage : DIOT_pkg
hdl/testbench/diot_test/bases.sv
View file @ c4b3209c
//TODO transfer transactions through channels
///////////////////////////////////////////////////////////////////////////////
// Title : DIOT WIC testbench top
// Project : Distributed I/O Tier
///////////////////////////////////////////////////////////////////////////////
// File : bases.vhd
// Author : Denia Bouhired <denia.bouhired@cern.ch>
// Company : CERN (BE-CO-HT)
// Standard : VHDL
///////////////////////////////////////////////////////////////////////////////
// Description:
// Generic base classes for DIOT/WIC testbench
//
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2018 CERN
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”) (which enables you, at your option,
// to treat this file as licensed under the Apache License 2.0); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//
///////////////////////////////////////////////////////////////////////////////
// bases.sv
`ifndef BASES__SV
`define BASES__SV
typedef class DIOT_stimulus_gen; //forward type definition
typedef t_dir;
class DIOT_trans; // parent class
rand int slot; //slot number of destination peripheral
const DIOT_stimulus_gen owner;
t_dir dir;
byte unsigned payload [0:123];
constraint legal_slot {
slot >= 2;
slot <= 4;
}
function new(DIOT_stimulus_gen owner = null);
this.owner = owner;
this.payload='{124{'h00}};
$write("New transaction created ...");
endfunction : new
endclass
endclass
//typedef class WIC_trans;
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~//
//
......
hdl/testbench/diot_test/dut_harness.sv
View file @ c4b3209c
///////////////////////////////////////////////////////////////////////////////
// Title : DIOT WIC testbench DUT harness
// Project : Distributed I/O Tier
///////////////////////////////////////////////////////////////////////////////
// File : dut_harness.vhd
// Author : Denia Bouhired <denia.bouhired@cern.ch>
// Company : CERN (BE-CO-HT)
// Standard : VHDL
///////////////////////////////////////////////////////////////////////////////
// Description:
// DIOT/WIC testbench - Harness containing an interface talking worldFIP to a
// nanoFIP/DIOT system board DUT running a WIC application
//
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2018 CERN
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”) (which enables you, at your option,
// to treat this file as licensed under the Apache License 2.0); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
`include "fip_phy_model.svh"
`include "fip_frame.svh"
`include "fip_hardware_model.svh"
//`include "tb_hook.svh"
interface tb_wb_hook (input bit clk); //wishbone hook
// Backplane/System board diagnostics interface
interface backplane_if (); //backplane interface
wire rstpo_n, diag_sda, diag_scl;
// TODO ?
// clocking cb @(posedge clk);
// endclocking : cb
//modport tb_wb_from_nf
//modport tb_wb_to_nf
endinterface
// FMC/System board WB interface
interface wb_if (input bit clk); //wishbone hook
wire [15:0] wb_dat_in;
wire [15:0] wb_dat_out;
wire [9:0] wb_adr;
wire wb_stb, wclk, wb_we, wb_cyc, wb_ack, wb_rst;
// TODO
// clocking cb @(posedge clk);
// endclocking : cb
//modport tb_wb_from_nf
//modport tb_wb_to_nf
// TODO ?
// clocking cb @(posedge clk);
// endclocking : cb
//modport tb_wb_from_nf
//modport tb_wb_to_nf
endinterface
interface tb_nf_hook (input bit clk); //nanoFIP hook
// FMC/System board FIP interface
interface nf_fmc_if (input bit clk); //nanoFIP hook
wire nf_var1_acc, nf_var2_acc, nf_var3_acc;
wire nf_var1_rdy, nf_var2_rdy, nf_var3_rdy;
wire nf_nostat, nf_rst;
......@@ -35,16 +76,33 @@ interface tb_nf_hook (input bit clk); //nanoFIP hook
reg [7:0] nf_address = 8'h01; // Substation data
wire [2:0] nf_p3lgth;
reg input_data[0:123] = '{124{'h00}};
reg send_data = 0;
wire [7:0] output_data = 8'h00;
endinterface
interface tb_fd_hook (input bit clk); //nanoFIP hook
bit [7:0] payload[0:123] ;//= '{124{'h00}};
// reg send_data = 0;
// wire [7:0] output_data = 8'h00;
//Fieldrive and WFIP Master model
FIPBus fip_bus();
FieldriveFPGA fieldrive();
FieldriveModel fd_model(.fpga(fieldrive), .fip(fip_bus.fd));
FipPHY fip_master(.fip_p(fip_bus.bus.p), .fip_n(fip_bus.bus.n));
//------Define clocking block
// clocking cb @(posedge clk_40m);
// input nf_var3_rdy, nf_var2_rdy nf_var1_rdy
// output nf_rst, nf_nostat, nf_var3_acc, nf_var2_acc nf_var1_acc nf_p3lgth
// endclocking
task automatic sendFIPframe (uint8_t payload[$]);
FipFrame fip_frame;
fieldrive.speed = 'h01; //1Mbps
fip_master.setSpeed(1000000);
fip_master.setVerbose(1);
// fip_master.setVerbose(1);
#10us; // wait for reset
fip_frame = FipFrame::makeMF_ID_DAT('h05, DUT_nf_if.nf_address);
......@@ -52,22 +110,34 @@ task automatic sendFIPframe (uint8_t payload[$]);
#50us; // silence time
fip_frame = FipFrame::makeMF_RP_DAT(payload);
// fip_frame = FipFrame::makeMF_RP_DAT('{'h01, 'h02, 'h03, 'h04, 'h05, 'h06, 'h07, 'h08});
//fip_frame = FipFrame::makeMF_RP_DAT('{'h01, 'h02, 'h03, 'h04, 'h05, 'h06, 'h07, 'h08});
fip_master.sendFrame(fip_frame);
#100us; // silence time
// fip_frame = FipFrame::makeMF_RP_DAT({DUT_nf_if.input_data});
// fip_master.sendFrame(fip_frame);
// DUT_nf_if.send_data = 0;
endtask
function automatic getRxStatus ();
return fip_master.rx_idle;
endfunction
task automatic getFIPframe ();
FipFrame fip_frame;
fip_frame = FipFrame::makeMF_ID_DAT('h06, DUT_nf_if.nf_address);
fip_master.sendFrame(fip_frame);
#500us;
endtask;
task automatic dispFIPframe ();
// if (!getRxStatus())
$display("oN INTERFACE Received data is %p", fip_master.frame_data);
endtask
task automatic storeFIPframe ();
//if (!getRxStatus())
payload=fip_master.frame_data;
endtask
//TODO
// clocking cb @(posedge clk);
......@@ -78,11 +148,6 @@ endinterface
module dut_harness;
//Fieldrive and WFIP Master model
FIPBus fip_bus();
FieldriveFPGA fieldrive();
FieldriveModel fd_model(.fpga(fieldrive), .fip(fip_bus.fd));
FipPHY fip_master(.fip_p(fip_bus.bus.p), .fip_n(fip_bus.bus.n));
reg clk_125m_p = 0; // could be bit?
reg clk_125m_n = 1; // could be bit?
......@@ -91,8 +156,10 @@ module dut_harness;
reg clk_40m = 0;
always #(12500ps) clk_40m <= ~clk_40m;
tb_wb_hook DUT_wb_if(.clk(clk_125m_p));
tb_nf_hook DUT_nf_if(.clk(clk_125m_p));
wb_if DUT_wb_if(.clk(clk_125m_p));
nf_fmc_if DUT_nf_if(.clk(clk_40m));
tb_fd_hook DUT_fd_if(.clk(clk_40m));
backplane_if pentair_if();
// power-on-reset
reg rstpo_n = 0;
......@@ -126,20 +193,20 @@ module dut_harness;
.var1_rdy_i (DUT_nf_if.nf_var1_rdy),
.p3_lgth_o (DUT_nf_if.nf_p3lgth),
.diag_scl_b (diag_scl),
.diag_sda_b (diag_sda));
.diag_scl_b (pentair_if.diag_scl),
.diag_sda_b (pentair_if.diag_sda));
//------------------------------------------------
nanofip NF(
.c_id_i (4'hc), // Constructor field
.m_id_i (4'ha), // Model field
.p3_lgth_i (DUT_nf_if.nf_p3lgth),
.rate_i (fieldrive.speed),
.rate_i (DUT_fd_if.fieldrive.speed),
.subs_i (DUT_nf_if.nf_address), // Station address
.nostat_i (DUT_nf_if.nf_nostat),
.rstin_i (DUT_nf_if.nf_rst),
.rston_o (), // Reset output
.rstpon_i (rstpo_n),// Power-on-reset
.rstpon_i (pentair_if.rstpo_n),// Power-on-reset
.slone_i (1'b0), // Disable standalone mode
.uclk_i (clk_40m), // 40MHz clock
......@@ -163,16 +230,16 @@ module dut_harness;
.rst_i (DUT_wb_if.wb_rst),
// Receiver
.fd_rxcdn_i(fieldrive.fd_rxcdn),
.fd_rxd_i (fieldrive.fd_rxd),
.fd_txer_i (fieldrive.fd_txer),
.fd_wdgn_i (fieldrive.fd_wdgn),
.fd_rxcdn_i(DUT_fd_if.fieldrive.fd_rxcdn),
.fd_rxd_i (DUT_fd_if.fieldrive.fd_rxd),
.fd_txer_i (DUT_fd_if.fieldrive.fd_txer),
.fd_wdgn_i (DUT_fd_if.fieldrive.fd_wdgn),
// Transmitter
.fd_rstn_o (fieldrive.fd_rstn),
.fd_txck_o (fieldrive.fd_txck),
.fd_txd_o (fieldrive.fd_txd),
.fd_txena_o(fieldrive.fd_txena),
.fd_rstn_o (DUT_fd_if.fieldrive.fd_rstn),
.fd_txck_o (DUT_fd_if.fieldrive.fd_txck),
.fd_txd_o (DUT_fd_if.fieldrive.fd_txd),
.fd_txena_o(DUT_fd_if.fieldrive.fd_txena),
.r_fcser_o (),
.r_tler_o (),
......@@ -187,12 +254,10 @@ module dut_harness;
);
pentair_fcm2_model sim_FCM2(
.clk_i(wclk),
.rst_n_i(rstpo_n),
.sda_b(diag_sda),
.scl_b(diag_scl));
.clk_i(DUT_wb_if.wclk),
.rst_n_i(pentair_if.rstpo_n),
.sda_b(pentair_if.diag_sda),
.scl_b(pentair_if.diag_scl));
endmodule
hdl/testbench/diot_test/tb_top.sv
View file @ c4b3209c
`timescale 1ns/1ps
///////////////////////////////////////////////////////////////////////////////
// Title : DIOT WIC testbench top file
// Project : Distributed I/O Tier
///////////////////////////////////////////////////////////////////////////////
// File : tb_top.vhd
// Author : Denia Bouhired <denia.bouhired@cern.ch>
// Company : CERN (BE-CO-HT)
// Standard : VHDL
///////////////////////////////////////////////////////////////////////////////
// Description:
// DIOT/WIC testbench top file
//
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2018 CERN
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”) (which enables you, at your option,
// to treat this file as licensed under the Apache License 2.0); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//
///////////////////////////////////////////////////////////////////////////////
// `include "fip_phy_model.svh"
`timescale 1ns/1ps
`include "fip_frame.svh"
// `include "fip_hardware_model.svh"
module tb_top;
import DIOT_pkg :: *;
// FIPBus fip_bus();
// FieldriveFPGA fieldrive();
// FieldriveModel fd_model(.fpga(fieldrive), .fip(fip_bus.fd));
// FipPHY fip_master(.fip_p(fip_bus.bus.p), .fip_n(fip_bus.bus.n));
dut_harness harness();
function int DIO_lower_bound (int slot);
DIO_lower_bound = slot*4-4;
endfunction
function int DIO_higher_bound (int slot);
DIO_higher_bound = slot*4-1;
endfunction
initial begin
// FipFrame fip_frame;
automatic uint8_t payload[0:123] = '{124{'h00}};
tb_env env;
//DIO_trans test_trans;
int low_byte, high_byte;
$display("Testbench starting...");
#10us; // wait for reset
//-------------------------------------------
env = new (3, harness.DUT_wb_if, harness.DUT_nf_if);
//test_trans = new(env.gen);
//env.gen.current_temp = test_trans;
for (int j=0; j<3; j++) begin
env = new (4, harness.DUT_nf_if, harness.DUT_fd_if);
for (int j=0; j<5; j++) begin
$display("=====================");
$display("Cycle ", j);
// env.gen.flush;//payload[0:123] = '{124{'h00}};
env.run(3);
$display ("Next payload is %p", env.gen.DIO_payload[0:31] );
// $display ("Next payload is %p", env.gen.current_temp.payload[0:31] );
harness.DUT_nf_if.getFIPframe ();
env.run(5);
$display ("Next payload is %p", env.gen.DIO_payload[0:31] );
#5ms; // silence time
#500us; // silence time
end
......
hdl/testbench/diot_test/wave.do
View file @ c4b3209c
......@@ -40,6 +40,7 @@ add wave -noupdate -expand -group WIC_MAIN -radix hexadecimal /tb_top/harness/DU
add wave -noupdate -expand -group WIC_MAIN /tb_top/harness/DUT/cmp_wic_main/wb_dat_o
add wave -noupdate -expand -group WIC_MAIN -radix unsigned /tb_top/harness/DUT/cmp_wic_main/rd_size
add wave -noupdate -expand -group WIC_MAIN -radix hexadecimal /tb_top/harness/DUT/cmp_wic_main/rd_cnt
add wave -position 30 sim:/tb_top/harness/fip_master/rx_idle
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {263193277 ps} 0}
configure wave -namecolwidth 229
......
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