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bpm-sw
Commit 9ec11089 authored by Lucas Russo's avatar Lucas Russo
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Merge branch 'afcv3_port' into smio_fmc130m_active

parents f0f272d6 69a6eb75
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Showing with 517 additions and 126 deletions
.ycm_extra_conf.py
View file @ 9ec11089
......@@ -100,10 +100,20 @@ flags = [
'-I',
'hal/sm_io/modules',
'-I',
'hal/sm_io/rw_param',
'-I',
'hal/sm_io/modules/fmc130m_4ch',
'-I',
'hal/sm_io/modules/acq',
'-I',
'hal/sm_io/modules/dsp',
'-I',
'hal/sm_io/modules/swap',
'-I',
'hal/sm_io/protocols',
'-I',
'hal/sm_io/protocols/ops',
'-I',
'hal/msg',
'-I',
'hal/msg/smio_thsafe_ops',
......
Makefile
View file @ 9ec11089
......@@ -11,8 +11,8 @@ OBJCOPY = $(CROSS_COMPILE)objcopy
SIZE = $(CROSS_COMPILE)size
MAKE = make
# Select board in which we will work. Options are: ml605, afc
BOARD = ml605
# Select board in which we will work. Options are: ml605 or afcv3
BOARD ?= ml605
INSTALL_DIR ?= /usr/local
export INSTALL_DIR
......@@ -31,6 +31,14 @@ LIBCLIENT_DIR=libclient
# General C flags
CFLAGS = -std=gnu99 -O2 -DWR_SHIFT=2
ifeq ($(BOARD),ml605)
CFLAGS += -D__BOARD_ML605__
endif
ifeq ($(BOARD),afcv3)
CFLAGS += -D__BOARD_AFCV3__
endif
LOCAL_MSG_DBG ?= n
DBE_DBG ?= n
CFLAGS_DEBUG =
......
hal/boards/afcv3/board.h 0 → 100644
View file @ 9ec11089
#ifndef _BOARD_H_
#define _BOARD_H_
#include <mem_layout/afcv3/mem_layout.h>
/****************************/
/* General Definitions */
/****************************/
/* CPU Clock frequency in hertz */
#define SYS_CLOCK 100000000ULL
/* Baud rate of the builtin UART (does not apply to the VUART) */
#define UART_BAUDRATE 115200ULL
int board_init();
int board_update();
#endif
hal/dev_io/dev_io.c
View file @ 9ec11089
......@@ -7,9 +7,12 @@
#include "dev_io.h"
#include "debug_print.h"
#include "ll_io_utils.h"
#include "board.h"
#define DEVIO_SERVICE_LEN 50
static devio_err_e spwan_platform_smios (devio_t *devio);
void print_help (char *program_name)
{
printf( "Usage: %s [options]\n"
......@@ -158,33 +161,9 @@ int main (int argc, char *argv[])
free (*str_p);
broker_endp = NULL;
uint32_t fmc130m_4ch_id = 0x7085ef15;
uint32_t acq_id = 0x4519a0ad;
uint32_t dsp_id = 0x1bafbf1e;
uint32_t swap_id = 0x12897592;
devio_err_e err;
err = devio_register_sm (devio, fmc130m_4ch_id, NULL);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[dev_io] devio_register_sm error!\n");
goto err_devio;
}
err = devio_register_sm (devio, acq_id, NULL);
devio_err_e err = spwan_platform_smios (devio);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[dev_io] devio_register_sm error!\n");
goto err_devio;
}
err = devio_register_sm (devio, dsp_id, NULL);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[dev_io] devio_register_sm error!\n");
goto err_devio;
}
err = devio_register_sm (devio, swap_id, NULL);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[dev_io] devio_register_sm error!\n");
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[dev_io] spwan_platform_smios error!\n");
goto err_devio;
}
......@@ -224,3 +203,70 @@ err_exit:
free (*str_p);
return 0;
}
static devio_err_e spwan_platform_smios (devio_t *devio)
{
assert (devio);
uint32_t fmc130m_4ch_id = 0x7085ef15;
uint32_t acq_id = 0x4519a0ad;
uint32_t dsp_id = 0x1bafbf1e;
uint32_t swap_id = 0x12897592;
devio_err_e err;
/* ML605 or AFCv3 */
#if defined (__BOARD_ML605__) || defined (__BOARD_AFCV3__)
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_INFO, "[dev_io] Spawning default SMIOs ...\n");
err = devio_register_sm (devio, fmc130m_4ch_id, FMC1_130M_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[dev_io] devio_register_sm error!\n");
goto err_register_sm;
}
err = devio_register_sm (devio, acq_id, WB_ACQ_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[dev_io] devio_register_sm error!\n");
goto err_register_sm;
}
err = devio_register_sm (devio, dsp_id, DSP1_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[dev_io] devio_register_sm error!\n");
goto err_register_sm;
}
err = devio_register_sm (devio, swap_id, DSP1_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[dev_io] devio_register_sm error!\n");
goto err_register_sm;
}
/* AFCv3 spefific */
#if defined (__BOARD_AFCV3__)
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_INFO, "[dev_io] Spawning AFCv3 specific SMIOs ...\n");
err = devio_register_sm (devio, fmc130m_4ch_id, FMC2_130M_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[dev_io] devio_register_sm error!\n");
goto err_register_sm;
}
err = devio_register_sm (devio, dsp_id, DSP2_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[dev_io] devio_register_sm error!\n");
goto err_register_sm;
}
err = devio_register_sm (devio, swap_id, DSP2_BASE_ADDR, 0);
if (err != DEVIO_SUCCESS) {
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_FATAL, "[dev_io] devio_register_sm error!\n");
goto err_register_sm;
}
#endif
#else
#error "Board not supported!"
#endif
err_register_sm:
return err;
}
hal/dev_io/dev_io_core.c
View file @ 9ec11089
......@@ -52,9 +52,8 @@ static void _devio_destroy_smio (devio_t *self, uint32_t smio_id);
static void _devio_destroy_smio_all (devio_t *self);
/* Creates a new instance of Device Information */
devio_t * devio_new (char *name, char *endpoint_dev,
llio_type_e type, char *endpoint_broker, int verbose,
const char *log_file_name)
devio_t * devio_new (char *name, char *endpoint_dev, llio_type_e type,
char *endpoint_broker, int verbose, const char *log_file_name)
{
assert (name);
assert (endpoint_dev);
......@@ -224,7 +223,8 @@ devio_err_e devio_print_info (devio_t *self)
}
/* Register an specific sm_io modules to this device */
devio_err_e devio_register_sm (devio_t *self, uint32_t smio_id, void *priv)
devio_err_e devio_register_sm (devio_t *self, uint32_t smio_id, uint32_t base,
uint32_t inst_id)
{
assert (self);
......@@ -270,7 +270,8 @@ devio_err_e devio_register_sm (devio_t *self, uint32_t smio_id, void *priv)
th_args->broker = self->endpoint_broker;
th_args->service = self->name;
th_args->verbose = self->verbose;
th_args->priv = priv;
th_args->base = base;
th_args->inst_id = inst_id;
DBE_DEBUG (DBG_DEV_IO | DBG_LVL_TRACE,
"[dev_io_core:register_sm] Calling boot func\n");
......@@ -313,6 +314,7 @@ devio_err_e devio_register_sm (devio_t *self, uint32_t smio_id, void *priv)
th_config_args->smio_id = i;
th_config_args->service = self->name;
th_config_args->log_file = self->log_file;
th_config_args->inst_id = inst_id;
config_pipe = zthread_fork (self->ctx, smio_config_defaults, th_config_args);
ASSERT_TEST (config_pipe != NULL, "Could not spawn config thread",
......@@ -351,10 +353,11 @@ devio_err_e devio_register_all_sm (devio_t *self)
return DEVIO_ERR_FUNC_NOT_IMPL;
}
devio_err_e devio_unregister_sm (devio_t *self, uint32_t smio_id)
devio_err_e devio_unregister_sm (devio_t *self, uint32_t smio_id, uint32_t inst_id)
{
(void) self;
(void) smio_id;
(void) inst_id;
return DEVIO_ERR_FUNC_NOT_IMPL;
}
......
hal/dev_io/dev_io_core.h
View file @ 9ec11089
......@@ -94,11 +94,12 @@ devio_err_e devio_destroy (devio_t **self_p);
* this is stored in the SDB structure inside the device */
devio_err_e devio_print_info (devio_t *self);
/* Register an specific sm_io module to this device */
devio_err_e devio_register_sm (devio_t *self, uint32_t smio_id, void *priv);
devio_err_e devio_register_sm (devio_t *self, uint32_t smio_id, uint32_t base,
uint32_t inst_id);
/* Register all sm_io module that this device can handle,
* according to the device information stored in the SDB */
devio_err_e devio_register_all_sm (devio_t *self);
devio_err_e devio_unregister_sm (devio_t *self, uint32_t smio_id);
devio_err_e devio_unregister_sm (devio_t *self, uint32_t smio_id, uint32_t inst_id);
devio_err_e devio_unregister_all_sm (devio_t *self);
/* Initilize poller with all of the initialized PIPE sockets */
devio_err_e devio_init_poller_sm (devio_t *self);
......
hal/hal_utils/hal_utils.c
View file @ 9ec11089
......@@ -35,6 +35,9 @@
CHECK_HAL_ERR(err, HAL_UTILS, "[halutils]", \
halutils_err_str (err_type))
static char *_halutils_concat_strings_raw (const char *str1, const char* str2,
const char *str3, char sep);
uint32_t num_to_str_len (uint32_t key, uint32_t base)
{
uint32_t i = 0;
......@@ -86,15 +89,41 @@ char *halutils_stringify_hex_key (uint32_t key)
}
#define SEPARATOR_BYTES 1
char *halutils_concat_strings (const char *str1, const char* str2, char sep)
/* FIXME: poorly written */
static char *_halutils_concat_strings_raw (const char *str1, const char* str2,
const char *str3, char sep)
{
char *str = zmalloc (strlen(str1) + strlen(str2) +
SEPARATOR_BYTES /* separator length */+ 1 /* \0 */);
ASSERT_ALLOC(str, err_str_alloc);
sprintf (str, "%s%c%s", str1, sep, str2);
assert (str1);
assert (str2);
char *str = NULL;
if (str3 != NULL) {
str = zmalloc (strlen (str1) + strlen (str2) + strlen (str3) +
SEPARATOR_BYTES /* separator length */+ 1 /* \0 */);
ASSERT_ALLOC(str, err_str3_alloc);
sprintf (str, "%s%c%s%s", str1, sep, str2, str3);
}
else {
str = zmalloc (strlen(str1) + strlen(str2) +
SEPARATOR_BYTES /* separator length */+ 1 /* \0 */);
ASSERT_ALLOC(str, err_str2_alloc);
sprintf (str, "%s%c%s", str1, sep, str2);
}
return str;
err_str_alloc:
err_str3_alloc:
err_str2_alloc:
return NULL;
}
char *halutils_concat_strings (const char *str1, const char* str2, char sep)
{
return _halutils_concat_strings_raw (str1, str2, NULL, sep);
}
char *halutils_concat_strings3 (const char *str1, const char* str2,
const char* str3, char sep)
{
return _halutils_concat_strings_raw (str1, str2, str3, sep);
}
hal/hal_utils/hal_utils.h
View file @ 9ec11089
......@@ -35,4 +35,9 @@ char *halutils_stringify_hex_key (uint32_t key);
* OK, NULL in case of error */
char *halutils_concat_strings (const char *str1, const char* str2, char sep);
/* Concatenates 3 strings togheter with a separator between the first and second
* strings. returns the string if OK, NULL in case of error */
char *halutils_concat_strings3 (const char *str1, const char* str2,
const char* str3, char sep);
#endif
hal/include/mem_layout/afcv3/mem_layout.h 0 → 100644
View file @ 9ec11089
#ifndef _MEM_LAYOUT_H_
#define _MEM_LAYOUT_H_
#include "pcie_regs.h"
/*********************** Static AFCv3 FPGA layout ***********************/
/* FMC_130M Components */
#define FMC_130M_CTRL_RAW_REGS_OFFS 0x0000
#define FMC_130M_SI571_RAW_I2C_OFFS 0x0100
#define FMC_130M_AD9510_RAW_SPI_OFFS 0x0200
#define FMC_130M_EEPROM_RAW_I2C_OFFS 0x0300
#define FMC_130M_LM75A_RAW_I2C_OFFS 0x0400
/* DSP Components */
#define DSP_CTRL_RAW_REGS_OFFS 0x0000
#define DSP_BPM_RAW_SWAP_OFFS 0x0100
/* Should be autodiscovered by SDB */
/* Wishbone RAW Addresses */
#define FMC1_130M_BASE_RAW_ADDR 0x00310000
#define FMC1_130M_CTRL_RAW_REGS (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_CTRL_RAW_REGS_OFFS)
#define FMC1_130M_SI571_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_SI571_RAW_I2C_OFFS)
#define FMC1_130M_AD9510_RAW_SPI (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_AD9510_RAW_SPI_OFFS)
#define FMC1_130M_EEPROM_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC1_130M_LM75A_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_LM75A_RAW_I2C_OFFS)
#define DSP1_BASE_RAW_ADDR 0x00308000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP1_BPM_RAW_SWAP (DSP1_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define FMC2_130M_BASE_RAW_ADDR 0x00350000
#define FMC2_130M_CTRL_RAW_REGS (FMC2_130M_BASE_RAW_ADDR + \
FMC_130M_CTRL_RAW_REGS_OFFS)
#define FMC2_130M_SI571_RAW_I2C (FMC2_130M_BASE_RAW_ADDR + \
FMC_130M_SI571_RAW_I2C_OFFS)
#define FMC2_130M_AD9510_RAW_SPI (FMC2_130M_BASE_RAW_ADDR + \
FMC_130M_AD9510_RAW_SPI_OFFS)
#define FMC2_130M_EEPROM_RAW_I2C (FMC2_130M_BASE_RAW_ADDR + \
FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC2_130M_LM75A_RAW_I2C (FMC2_130M_BASE_RAW_ADDR + \
FMC_130M_LM75A_RAW_I2C_OFFS)
#define DSP2_BASE_RAW_ADDR 0x00340000
#define DSP2_CTRL_RAW_REGS (DSP2_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP2_BPM_RAW_SWAP (DSP2_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define WB_ACQ_BASE_RAW_ADDR 0x00330000
/* Large Memory RAW Addresses. It lives at address 0 */
#define LARGE_MEM_RAW_ADDR 0x00000000
/* The following is a bit of a hack.
* We employ a generic API for talking to the hardware.
* So, our transport layer (PCIe or Ethernet, for now)
* should be invisible to the SMIO instances.
*
* However, PCI devices generally employ multiple BAR
* registers mapped to different parts of the device.
* For instance, in the bpm-gw FPGA firmware, the PCIe
* core has 3 BARs (BAR0, BAR2 and BAR4) mapped to the
* following:
*
* BAR0 -> PCIe control registers
* BAR2 -> DDR3 SDRAM
* BAR4 -> Wishbone (necessary to use pages mechanism)
*
* So, we define our addresses as the logic address plus
* the BAR number. With this, the PCIe transport layer
* can differentiate between multiple bars and select
* the correct one to read or write
*/
/* FMC_130M Components */
#define FMC_130M_CTRL_REGS_OFFS (BAR4_ADDR | FMC_130M_CTRL_RAW_REGS_OFFS)
#define FMC_130M_SI571_I2C_OFFS (BAR4_ADDR | FMC_130M_SI571_I2C_RAW_OFFS)
#define FMC_130M_AD9510_SPI_OFFS (BAR4_ADDR | FMC_130M_AD9510_RAW_SPI_OFFS)
#define FMC_130M_EEPROM_I2C_OFFS (BAR4_ADDR | FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC_130M_LM75A_I2C_OFFS (BAR4_ADDR | FMC_130M_LM75A_RAW_I2C_OFFS)
/* DSP Components */
#define DSP_CTRL_REGS_OFFS (BAR4_ADDR | DSP_CTRL_RAW_REGS_OFFS)
#define DSP_BPM_SWAP_OFFS (BAR4_ADDR | DSP_BPM_RAW_SWAP_OFFS)
/* Wishbone Addresses */
#define FMC1_130M_BASE_ADDR (BAR4_ADDR | FMC1_130M_BASE_RAW_ADDR)
#define FMC1_130M_CTRL_REGS (BAR4_ADDR | FMC1_130M_CTRL_RAW_REGS)
#define FMC1_130M_SI571_I2C (BAR4_ADDR | FMC1_130M_SI571_RAW_I2C)
#define FMC1_130M_AD9510_SPI (BAR4_ADDR | FMC1_130M_AD9510_RAW_SPI)
#define FMC1_130M_EEPROM_I2C (BAR4_ADDR | FMC1_130M_EEPROM_RAW_I2C)
#define FMC1_130M_LM75A_I2C (BAR4_ADDR | FMC1_130M_LM75A_RAW_I2C)
#define DSP1_BASE_ADDR (BAR4_ADDR | DSP1_BASE_RAW_ADDR)
#define DSP1_CTRL_REGS (BAR4_ADDR | DSP1_CTRL_RAW_REGS)
#define DSP1_BPM_SWAP (BAR4_ADDR | DSP1_BPM_RAW_SWAP)
#define WB_ACQ_BASE_ADDR (BAR4_ADDR | WB_ACQ_BASE_RAW_ADDR)
#define FMC2_130M_BASE_ADDR (BAR4_ADDR | FMC2_130M_BASE_RAW_ADDR)
#define FMC2_130M_CTRL_REGS (BAR4_ADDR | FMC2_130M_CTRL_RAW_REGS)
#define FMC2_130M_SI571_I2C (BAR4_ADDR | FMC2_130M_SI571_RAW_I2C)
#define FMC2_130M_AD9510_SPI (BAR4_ADDR | FMC2_130M_AD9510_RAW_SPI)
#define FMC2_130M_EEPROM_I2C (BAR4_ADDR | FMC2_130M_EEPROM_RAW_I2C)
#define FMC2_130M_LM75A_I2C (BAR4_ADDR | FMC2_130M_LM75A_RAW_I2C)
#define DSP2_BASE_ADDR (BAR4_ADDR | DSP2_BASE_RAW_ADDR)
#define DSP2_CTRL_REGS (BAR4_ADDR | DSP2_CTRL_RAW_REGS)
#define DSP2_BPM_SWAP (BAR4_ADDR | DSP2_BPM_RAW_SWAP)
/* Large Memory Addresses */
#define LARGE_MEM_ADDR (BAR2_ADDR | LARGE_MEM_RAW_ADDR)
/************************* ML605 Gateware Options *************************/
/*********************** SMIO ACQ Gateware Options ***********************/
/* FIXME: The Gateware does not support yet a way of reading which
* ACQ channels are valid. So, we hardcoded it here for now. This issue
* should be addressed soon */
#define SMIO_ACQ_NUM_CHANNELS 5
#endif
hal/include/mem_layout/ml605/mem_layout.h
View file @ 9ec11089
......@@ -4,22 +4,39 @@
#include "pcie_regs.h"
/*********************** Static ML605 FPGA layout ***********************/
/* FMC_130M Components */
#define FMC_130M_CTRL_RAW_REGS_OFFS 0x0000
#define FMC_130M_SI571_RAW_I2C_OFFS 0x0100
#define FMC_130M_AD9510_RAW_SPI_OFFS 0x0200
#define FMC_130M_EEPROM_RAW_I2C_OFFS 0x0300
#define FMC_130M_LM75A_RAW_I2C_OFFS 0x0400
/* DSP Components */
#define DSP_CTRL_RAW_REGS_OFFS 0x0000
#define DSP_BPM_RAW_SWAP_OFFS 0x0100
/* Should be autodiscovered by SDB */
/* Wishbone RAW Addresses */
#define FMC130M_BASE_RAW_ADDR 0x00310000
#define FPGA_CTRL_RAW_REGS (FMC130M_BASE_RAW_ADDR + 0x0000)
#define FPGA_SI571_RAW_I2C (FMC130M_BASE_RAW_ADDR + 0x0100)
#define FPGA_AD9510_RAW_SPI (FMC130M_BASE_RAW_ADDR + 0x0200)
#define FPGA_EEPROM_RAW_I2C (FMC130M_BASE_RAW_ADDR + 0x0300)
#define FPGA_LM75A_RAW_I2C (FMC130M_BASE_RAW_ADDR + 0x0400)
#define DSP_BASE_RAW_ADDR 0x00308000
#define DSP_CTRL_RAW_REGS (DSP_BASE_RAW_ADDR + 0x00000000)
#define DSP_BPM_RAW_SWAP (DSP_BASE_RAW_ADDR + 0x00000100)
#define FMC1_130M_BASE_RAW_ADDR 0x00310000
#define FMC1_130M_CTRL_RAW_REGS (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_CTRL_RAW_REGS_OFFS)
#define FMC1_130M_SI571_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_SI571_RAW_I2C_OFFS)
#define FMC1_130M_AD9510_RAW_SPI (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_AD9510_RAW_SPI_OFFS)
#define FMC1_130M_EEPROM_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC1_130M_LM75A_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_LM75A_RAW_I2C_OFFS)
#define DSP1_BASE_RAW_ADDR 0x00308000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP1_BPM_RAW_SWAP (DSP1_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define WB_ACQ_BASE_RAW_ADDR 0x00330000
......@@ -47,19 +64,30 @@
* the correct one to read or write
*/
/* FMC_130M Components */
#define FMC_130M_CTRL_REGS_OFFS (BAR4_ADDR | FMC_130M_CTRL_RAW_REGS_OFFS)
#define FMC_130M_SI571_I2C_OFFS (BAR4_ADDR | FMC_130M_SI571_I2C_RAW_OFFS)
#define FMC_130M_AD9510_SPI_OFFS (BAR4_ADDR | FMC_130M_AD9510_RAW_SPI_OFFS)
#define FMC_130M_EEPROM_I2C_OFFS (BAR4_ADDR | FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC_130M_LM75A_I2C_OFFS (BAR4_ADDR | FMC_130M_LM75A_RAW_I2C_OFFS)
/* DSP Components */
#define DSP_CTRL_REGS_OFFS (BAR4_ADDR | DSP_CTRL_RAW_REGS_OFFS)
#define DSP_BPM_SWAP_OFFS (BAR4_ADDR | DSP_BPM_RAW_SWAP_OFFS)
/* Wishbone Addresses */
#define FMC130M_BASE_ADDR (BAR4_ADDR | FMC130M_BASE_RAW_ADDR)
#define FMC1_130M_BASE_ADDR (BAR4_ADDR | FMC1_130M_BASE_RAW_ADDR)
#define FPGA_CTRL_REGS (BAR4_ADDR | FPGA_CTRL_RAW_REGS)
#define FPGA_SI571_I2C (BAR4_ADDR | FPGA_SI571_RAW_I2C)
#define FPGA_AD9510_SPI (BAR4_ADDR | FPGA_AD9510_RAW_SPI)
#define FPGA_EEPROM_I2C (BAR4_ADDR | FPGA_EEPROM_RAW_I2C)
#define FPGA_LM75A_I2C (BAR4_ADDR | FPGA_LM75A_RAW_I2C)
#define FMC1_130M_CTRL_REGS (BAR4_ADDR | FMC1_130M_CTRL_RAW_REGS)
#define FMC1_130M_SI571_I2C (BAR4_ADDR | FMC1_130M_SI571_RAW_I2C)
#define FMC1_130M_AD9510_SPI (BAR4_ADDR | FMC1_130M_AD9510_RAW_SPI)
#define FMC1_130M_EEPROM_I2C (BAR4_ADDR | FMC1_130M_EEPROM_RAW_I2C)
#define FMC1_130M_LM75A_I2C (BAR4_ADDR | FMC1_130M_LM75A_RAW_I2C)
#define DSP_BASE_ADDR (BAR4_ADDR | DSP_BASE_RAW_ADDR)
#define DSP1_BASE_ADDR (BAR4_ADDR | DSP1_BASE_RAW_ADDR)
#define DSP_CTRL_REGS (BAR4_ADDR | DSP_CTRL_RAW_REGS)
#define DSP_BPM_SWAP (BAR4_ADDR | DSP_BPM_RAW_SWAP)
#define DSP1_CTRL_REGS (BAR4_ADDR | DSP1_CTRL_RAW_REGS)
#define DSP1_BPM_SWAP (BAR4_ADDR | DSP1_BPM_RAW_SWAP)
#define WB_ACQ_BASE_ADDR (BAR4_ADDR | WB_ACQ_BASE_RAW_ADDR)
......
hal/sm_io/modules/acq/sm_io_acq_exp.c
View file @ 9ec11089
......@@ -145,8 +145,7 @@ static void *_acq_data_acquire (void *owner, void *args)
uint32_t acq_core_shots = ACQ_CORE_SHOTS_NB_W(1);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:acq] data_acquire: "
"Number of shots = %u\n", acq_core_shots);
smio_thsafe_client_write_32 (self, WB_ACQ_BASE_ADDR |
ACQ_CORE_REG_SHOTS, &acq_core_shots);
smio_thsafe_client_write_32 (self, ACQ_CORE_REG_SHOTS, &acq_core_shots);
/* FIXME FPGA Firmware requires number of samples to be divisible by
* acquisition channel sample size */
......@@ -158,45 +157,39 @@ static void *_acq_data_acquire (void *owner, void *args)
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:acq] data_acquire: "
"Number of pre-trigger samples (aligned to sample size) = %u\n",
num_samples_aligned_pre);
smio_thsafe_client_write_32 (self, WB_ACQ_BASE_ADDR |
ACQ_CORE_REG_PRE_SAMPLES, &num_samples_aligned_pre);
smio_thsafe_client_write_32 (self, ACQ_CORE_REG_PRE_SAMPLES, &num_samples_aligned_pre);
/* Post trigger samples */
uint32_t num_samples_post = 0;
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:acq] data_acquire: "
"Number of post-trigger samples = %u\n",
num_samples_post);
smio_thsafe_client_write_32 (self, WB_ACQ_BASE_ADDR |
ACQ_CORE_REG_POST_SAMPLES, &num_samples_post);
smio_thsafe_client_write_32 (self, ACQ_CORE_REG_POST_SAMPLES, &num_samples_post);
/* DDR3 start address */
uint32_t start_addr = (uint32_t) SMIO_ACQ_HANDLER(self)->acq_buf[chan].start_addr;
uint32_t start_addr8 = start_addr/8;
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:acq] data_acquire: "
"DDR3 start address: 0x%08x\n", start_addr);
smio_thsafe_client_write_32 (self, WB_ACQ_BASE_ADDR |
ACQ_CORE_REG_DDR3_START_ADDR, &start_addr8 );
smio_thsafe_client_write_32 (self, ACQ_CORE_REG_DDR3_START_ADDR, &start_addr8 );
/* Prepare core_ctl register */
uint32_t acq_core_ctl_reg = ACQ_CORE_CTL_FSM_ACQ_NOW;
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:acq] data_acquire: "
"Control register is: 0x%08x\n",
acq_core_ctl_reg);
smio_thsafe_client_write_32 (self, WB_ACQ_BASE_ADDR |
ACQ_CORE_REG_CTL, &acq_core_ctl_reg );
smio_thsafe_client_write_32 (self, ACQ_CORE_REG_CTL, &acq_core_ctl_reg );
/* Prepare acquisition channel control */
uint32_t acq_chan_ctl = ACQ_CORE_ACQ_CHAN_CTL_WHICH_W(chan);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:acq] data_acquire: "
"Channel control register is: 0x%08x\n",
acq_chan_ctl);
smio_thsafe_client_write_32 (self, WB_ACQ_BASE_ADDR |
ACQ_CORE_REG_ACQ_CHAN_CTL, &acq_chan_ctl );
smio_thsafe_client_write_32 (self, ACQ_CORE_REG_ACQ_CHAN_CTL, &acq_chan_ctl );
/* Starting acquisition... */
acq_core_ctl_reg |= ACQ_CORE_CTL_FSM_START_ACQ;
smio_thsafe_client_write_32 (self, WB_ACQ_BASE_ADDR |
ACQ_CORE_REG_CTL, &acq_core_ctl_reg );
smio_thsafe_client_write_32 (self, ACQ_CORE_REG_CTL, &acq_core_ctl_reg );
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:acq] data_acquire: "
"Acquisition Started!\n");
......@@ -224,8 +217,7 @@ static void *_acq_check_data_acquire (void *owner, void *args)
uint32_t status_done = 0;
/* Check for completion */
smio_thsafe_client_read_32 (self, WB_ACQ_BASE_ADDR |
ACQ_CORE_REG_STA, &status_done );
smio_thsafe_client_read_32 (self, ACQ_CORE_REG_STA, &status_done );
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:acq] data_acquire: "
"Status done = 0x%08x\n", status_done);
......@@ -351,7 +343,9 @@ static void *_acq_get_data_block (void *owner, void *args)
/* static max allocation (32-bit words) */
uint32_t data_out[BLOCK_SIZE/sizeof(uint32_t)];
ssize_t bytes_read = smio_thsafe_client_read_block (self, LARGE_MEM_ADDR | addr_i,
/* Here we must use the "raw" version, as we can't have
* LARGE_MEM_ADDR mangled with the bas address of this SMIO */
ssize_t bytes_read = smio_thsafe_raw_client_read_block (self, LARGE_MEM_ADDR | addr_i,
reply_size, data_out);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:acq] get_data_block: "
"%lu bytes read\n", bytes_read);
......
hal/sm_io/modules/dsp/sm_io_dsp_exp.c
View file @ 9ec11089
......@@ -48,42 +48,42 @@
#define KX_PARAM_MIN 1
#define KX_PARAM_MAX ((1<<25)-1)
RW_PARAM_FUNC(dsp, kx) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS, POS_CALC, KX, VAL, MULT_BIT_PARAM,
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, KX, VAL, MULT_BIT_PARAM,
KX_PARAM_MIN, KX_PARAM_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define KY_PARAM_MIN 1
#define KY_PARAM_MAX ((1<<25)-1)
RW_PARAM_FUNC(dsp, ky) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS, POS_CALC, KY, VAL, MULT_BIT_PARAM,
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, KY, VAL, MULT_BIT_PARAM,
KY_PARAM_MIN, KY_PARAM_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define KSUM_PARAM_MIN 1
#define KSUM_PARAM_MAX ((1<<25)-1)
RW_PARAM_FUNC(dsp, ksum) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS, POS_CALC, KSUM, VAL, MULT_BIT_PARAM,
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, KSUM, VAL, MULT_BIT_PARAM,
KSUM_PARAM_MIN, KSUM_PARAM_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define DS_TBT_THRES_MIN 0
#define DS_TBT_THRES_MAX ((1<<26)-1)
RW_PARAM_FUNC(dsp, ds_tbt_thres) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS, POS_CALC, DS_TBT_THRES, VAL, MULT_BIT_PARAM,
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DS_TBT_THRES, VAL, MULT_BIT_PARAM,
DS_TBT_THRES_MIN, DS_TBT_THRES_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define DS_FOFB_THRES_MIN 0
#define DS_FOFB_THRES_MAX ((1<<26)-1)
RW_PARAM_FUNC(dsp, ds_fofb_thres) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS, POS_CALC, DS_FOFB_THRES, VAL, MULT_BIT_PARAM,
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DS_FOFB_THRES, VAL, MULT_BIT_PARAM,
DS_FOFB_THRES_MIN, DS_FOFB_THRES_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define DS_MONIT_THRES_MIN 0
#define DS_MONIT_THRES_MAX ((1<<26)-1)
RW_PARAM_FUNC(dsp, ds_monit_thres) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS, POS_CALC, DS_MONIT_THRES, VAL, MULT_BIT_PARAM,
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DS_MONIT_THRES, VAL, MULT_BIT_PARAM,
DS_MONIT_THRES_MIN, DS_MONIT_THRES_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......
hal/sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_exp.c
View file @ 9ec11089
......@@ -13,6 +13,7 @@
#include "dev_io.h"
#include "board.h"
#include "hal_assert.h"
#include "wb_fmc130m_4ch_regs.h"
/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
#ifdef ASSERT_TEST
......@@ -37,8 +38,6 @@
CHECK_HAL_ERR(err, SM_IO, "[sm_io:fmc130m_4ch_exp]", \
smio_err_str (err_type))
#define FMC_MONITOR_REG (FMC130M_BASE_ADDR | 0x010)
/************************************************************/
/************ Specific FMC_130M_4CH Operations **************/
/************************************************************/
......@@ -54,7 +53,8 @@ static void *_fmc130m_4ch_leds (void *owner, void *args)
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc130m_4ch_exp] Calling _fmc130m_4ch_leds\n");
uint32_t leds = *(uint32_t *) zframe_data (zmsg_pop (*exp_msg->msg));
smio_thsafe_client_write_32 (self, FMC_MONITOR_REG, &leds);
smio_thsafe_client_write_32 (self, FMC_130M_CTRL_REGS_OFFS |
WB_FMC_130M_4CH_CSR_REG_MONITOR , &leds);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:fmc130m_4ch_exp] Led write: 0x%08x\n",
leds);
......
hal/sm_io/modules/swap/sm_io_swap_exp.c
View file @ 9ec11089
......@@ -57,21 +57,21 @@
#define BPM_SWAP_CTRL_MODE_GLOBAL_W(val) (BPM_SWAP_CTRL_MODE1_W(val) | BPM_SWAP_CTRL_MODE2_W(val))
#define BPM_SWAP_CTRL_MODE_GLOBAL_R(val) (BPM_SWAP_CTRL_MODE1_R(val) | BPM_SWAP_CTRL_MODE2_R(val))
RW_PARAM_FUNC(swap, sw) {
SET_GET_PARAM(swap, DSP_BPM_SWAP, BPM_SWAP, CTRL, MODE_GLOBAL, MULT_BIT_PARAM,
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, CTRL, MODE_GLOBAL, MULT_BIT_PARAM,
SW_MIN, SW_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define BPM_SW_EN_MIN 0 /* Switching enabled */
#define BPM_SW_EN_MAX 1 /* Switching disabled */
RW_PARAM_FUNC(swap, sw_en) {
SET_GET_PARAM(swap, DSP_BPM_SWAP, BPM_SWAP, CTRL, CLK_SWAP_EN, SINGLE_BIT_PARAM,
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, CTRL, CLK_SWAP_EN, SINGLE_BIT_PARAM,
BPM_SW_EN_MIN, BPM_SW_EN_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define BPM_SWAP_DIV_F_MIN 1
#define BPM_SWAP_DIV_F_MAX ((1<<16)-1)
RW_PARAM_FUNC(swap, div_clk) {
SET_GET_PARAM(swap, DSP_BPM_SWAP, BPM_SWAP, CTRL, SWAP_DIV_F, MULT_BIT_PARAM,
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, CTRL, SWAP_DIV_F, MULT_BIT_PARAM,
BPM_SWAP_DIV_F_MIN, BPM_SWAP_DIV_F_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -83,7 +83,7 @@ RW_PARAM_FUNC(swap, div_clk) {
#define BPM_SWAP_DLY_GLOBAL_W(val) (BPM_SWAP_DLY_1_W(val) | BPM_SWAP_DLY_2_W(val))
#define BPM_SWAP_DLY_GLOBAL_R(val) (BPM_SWAP_DLY_1_R(val) | BPM_SWAP_DLY_2_R(val))
RW_PARAM_FUNC(swap, sw_dly) {
SET_GET_PARAM(swap, DSP_BPM_SWAP, BPM_SWAP, DLY, GLOBAL, MULT_BIT_PARAM,
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, DLY, GLOBAL, MULT_BIT_PARAM,
BPM_SWAP_SW_DLY_MIN, BPM_SWAP_SW_DLY_MAX, NO_CHK_FUNC, NO_FMT_FUNC,
SET_FIELD);
}
......@@ -93,14 +93,14 @@ RW_PARAM_FUNC(swap, sw_dly) {
#define BPM_SWAP_WDW_CTL_EN_GLOBAL (BPM_SWAP_WDW_CTL_USE | BPM_SWAP_WDW_CTL_SWCLK_EXT)
RW_PARAM_FUNC(swap, wdw) {
SET_GET_PARAM(swap, DSP_BPM_SWAP, BPM_SWAP, WDW_CTL, EN_GLOBAL, SINGLE_BIT_PARAM,
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, WDW_CTL, EN_GLOBAL, SINGLE_BIT_PARAM,
BPM_SWAP_WDW_EN_MIN, BPM_SWAP_WDW_EN_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define BPM_SWAP_WDW_DLY_MIN 1
#define BPM_SWAP_WDW_DLY_MAX ((1<<16)-1)
RW_PARAM_FUNC(swap, wdw_dly) {
SET_GET_PARAM(swap, DSP_BPM_SWAP, BPM_SWAP, WDW_CTL, DLY, MULT_BIT_PARAM,
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, WDW_CTL, DLY, MULT_BIT_PARAM,
BPM_SWAP_WDW_DLY_MIN, BPM_SWAP_WDW_DLY_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -136,7 +136,7 @@ rw_param_check_fp rw_bpm_swap_gain_chk_fp = _rw_bpm_swap_gain_chk;
#define BPM_SWAP_A_GLOBAL_W(val) (val)
#define BPM_SWAP_A_GLOBAL_R(val) (val)
RW_PARAM_FUNC(swap, gain_a) {
SET_GET_PARAM(swap, DSP_BPM_SWAP, BPM_SWAP, A, GLOBAL, MULT_BIT_PARAM,
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, A, GLOBAL, MULT_BIT_PARAM,
BPM_SWAP_GAIN_MIN, BPM_SWAP_GAIN_MAX, rw_bpm_swap_gain_chk_fp,
NO_FMT_FUNC, SET_FIELD);
}
......@@ -145,7 +145,7 @@ RW_PARAM_FUNC(swap, gain_a) {
#define BPM_SWAP_B_GLOBAL_W(val) (val)
#define BPM_SWAP_B_GLOBAL_R(val) (val)
RW_PARAM_FUNC(swap, gain_b) {
SET_GET_PARAM(swap, DSP_BPM_SWAP, BPM_SWAP, B, GLOBAL, MULT_BIT_PARAM,
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, B, GLOBAL, MULT_BIT_PARAM,
BPM_SWAP_GAIN_MIN, BPM_SWAP_GAIN_MAX, rw_bpm_swap_gain_chk_fp,
NO_FMT_FUNC, SET_FIELD);
}
......@@ -154,7 +154,7 @@ RW_PARAM_FUNC(swap, gain_b) {
#define BPM_SWAP_C_GLOBAL_W(val) (val)
#define BPM_SWAP_C_GLOBAL_R(val) (val)
RW_PARAM_FUNC(swap, gain_c) {
SET_GET_PARAM(swap, DSP_BPM_SWAP, BPM_SWAP, C, GLOBAL, MULT_BIT_PARAM,
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, C, GLOBAL, MULT_BIT_PARAM,
BPM_SWAP_GAIN_MIN, BPM_SWAP_GAIN_MAX, rw_bpm_swap_gain_chk_fp,
NO_FMT_FUNC, SET_FIELD);
}
......@@ -163,7 +163,7 @@ RW_PARAM_FUNC(swap, gain_c) {
#define BPM_SWAP_D_GLOBAL_W(val) (val)
#define BPM_SWAP_D_GLOBAL_R(val) (val)
RW_PARAM_FUNC(swap, gain_d) {
SET_GET_PARAM(swap, DSP_BPM_SWAP, BPM_SWAP, D, GLOBAL, MULT_BIT_PARAM,
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, D, GLOBAL, MULT_BIT_PARAM,
BPM_SWAP_GAIN_MIN, BPM_SWAP_GAIN_MAX, rw_bpm_swap_gain_chk_fp,
NO_FMT_FUNC, SET_FIELD);
}
......
hal/sm_io/sm_io.c
View file @ 9ec11089
......@@ -42,12 +42,17 @@
} \
} while(0)
#define ASSERT_FUNC(func_name) \
do { \
assert (self); \
assert (self->thsafe_client_ops); \
CHECK_FUNC (self->thsafe_client_ops->func_name); \
} while(0)
/* Declare wrapper for all SMIO functions API */
#define SMIO_FUNC_WRAPPER(func_name, ...) \
{ \
assert (self); \
assert (self->thsafe_client_ops); \
CHECK_FUNC (self->thsafe_client_ops->func_name); \
ASSERT_FUNC(func_name); \
return self->thsafe_client_ops->func_name (self, ##__VA_ARGS__); \
}
......@@ -188,37 +193,105 @@ int smio_thsafe_client_release (smio_t *self, llio_endpoint_t *endpoint)
/**** Read data from device ****/
ssize_t smio_thsafe_client_read_16 (smio_t *self, loff_t offs, uint16_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_read_16, offs, data)
{
ASSERT_FUNC(thsafe_client_read_16);
return self->thsafe_client_ops->thsafe_client_read_16 (self, self->base | offs, data);
}
ssize_t smio_thsafe_client_read_32 (smio_t *self, loff_t offs, uint32_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_read_32, offs, data)
{
ASSERT_FUNC(thsafe_client_read_32);
return self->thsafe_client_ops->thsafe_client_read_32 (self, self->base | offs, data);
}
ssize_t smio_thsafe_client_read_64 (smio_t *self, loff_t offs, uint64_t *data)
{
ASSERT_FUNC(thsafe_client_read_64);
return self->thsafe_client_ops->thsafe_client_read_64 (self, self->base | offs, data);
}
ssize_t smio_thsafe_raw_client_read_16 (smio_t *self, loff_t offs, uint16_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_read_16, offs, data)
ssize_t smio_thsafe_raw_client_read_32 (smio_t *self, loff_t offs, uint32_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_read_32, offs, data)
ssize_t smio_thsafe_raw_client_read_64 (smio_t *self, loff_t offs, uint64_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_read_64, offs, data)
/**** Write data to device ****/
ssize_t smio_thsafe_client_write_16 (smio_t *self, loff_t offs, const uint16_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_write_16, offs, data)
{
ASSERT_FUNC(thsafe_client_write_16);
return self->thsafe_client_ops->thsafe_client_write_16 (self, self->base | offs, data);
}
ssize_t smio_thsafe_client_write_32 (smio_t *self, loff_t offs, const uint32_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_write_32, offs, data)
{
ASSERT_FUNC(thsafe_client_write_32);
return self->thsafe_client_ops->thsafe_client_write_32 (self, self->base | offs, data);
}
ssize_t smio_thsafe_client_write_64 (smio_t *self, loff_t offs, const uint64_t *data)
{
ASSERT_FUNC(thsafe_client_write_64);
return self->thsafe_client_ops->thsafe_client_write_64 (self, self->base | offs, data);
}
ssize_t smio_thsafe_raw_client_write_16 (smio_t *self, loff_t offs, const uint16_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_write_16, offs, data)
ssize_t smio_thsafe_raw_client_write_32 (smio_t *self, loff_t offs, const uint32_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_write_32, offs, data)
ssize_t smio_thsafe_raw_client_write_64 (smio_t *self, loff_t offs, const uint64_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_write_64, offs, data)
/**** Read data block from device function pointer, size in bytes ****/
ssize_t smio_thsafe_client_read_block (smio_t *self, loff_t offs, size_t size, uint32_t *data)
ssize_t smio_thsafe_client_read_block (smio_t *self, loff_t offs, size_t size,
uint32_t *data)
{
ASSERT_FUNC(thsafe_client_read_block);
return self->thsafe_client_ops->thsafe_client_read_block (self, self->base | offs,
size, data);
}
ssize_t smio_thsafe_raw_client_read_block (smio_t *self, loff_t offs, size_t size, uint32_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_read_block, offs, size, data)
/**** Write data block from device function pointer, size in bytes ****/
ssize_t smio_thsafe_client_write_block (smio_t *self, loff_t offs, size_t size, const uint32_t *data)
ssize_t smio_thsafe_client_write_block (smio_t *self, loff_t offs, size_t size,
const uint32_t *data)
{
ASSERT_FUNC(thsafe_client_write_block);
return self->thsafe_client_ops->thsafe_client_write_block (self, self->base | offs,
size, data);
}
ssize_t smio_thsafe_raw_client_write_block (smio_t *self, loff_t offs, size_t size, const uint32_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_write_block, offs, size, data)
/**** Read data block via DMA from device, size in bytes ****/
ssize_t smio_thsafe_client_read_dma (smio_t *self, loff_t offs, size_t size, uint32_t *data)
ssize_t smio_thsafe_client_read_dma (smio_t *self, loff_t offs, size_t size,
uint32_t *data)
{
ASSERT_FUNC(thsafe_client_read_dma);
return self->thsafe_client_ops->thsafe_client_read_dma (self, self->base | offs,
size, data);
}
ssize_t smio_thsafe_raw_client_read_dma (smio_t *self, loff_t offs, size_t size, uint32_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_read_dma, offs, size, data)
/**** Write data block via DMA from device, size in bytes ****/
ssize_t smio_thsafe_client_write_dma (smio_t *self, loff_t offs, size_t size, const uint32_t *data)
ssize_t smio_thsafe_client_write_dma (smio_t *self, loff_t offs, size_t size,
const uint32_t *data)
{
ASSERT_FUNC(thsafe_client_write_dma);
return self->thsafe_client_ops->thsafe_client_write_dma (self, self->base | offs,
size, data);
}
ssize_t smio_thsafe_raw_client_write_dma (smio_t *self, loff_t offs, size_t size, const uint32_t *data)
SMIO_FUNC_WRAPPER (thsafe_client_write_dma, offs, size, data)
/**** Read device information function pointer ****/
/* int smio_thsafe_client_read_info (smio_t *self, llio_dev_info_t *dev_info)
/* int smio_thsafe_raw_client_read_info (smio_t *self, llio_dev_info_t *dev_info)
SMIO_FUNC_WRAPPER (thsafe_client_read_info, dev_info) Moved to dev_io */
hal/sm_io/sm_io.h
View file @ 9ec11089
......@@ -33,6 +33,7 @@ struct _smio_exp_ops_t;
struct _smio_t {
uint32_t id; /* Unique identifier for this sm_io type. This must be
the same from the SDB ID */
uint32_t base; /* Base SMIO address */
char *name; /* Identification of this sm_io instance */
char *service; /* Exported service name */
/* int verbose; */ /* Print activity to stdout */
......@@ -166,22 +167,45 @@ smio_err_e smio_do_op (void *owner, void *msg);
int smio_thsafe_client_open (smio_t *self, llio_endpoint_t *endpoint);
/* Release device */
int smio_thsafe_client_release (smio_t *self, llio_endpoint_t *endpoint);
/* Read data from device */
ssize_t smio_thsafe_client_read_16 (smio_t *self, loff_t offs, uint16_t *data);
ssize_t smio_thsafe_client_read_32 (smio_t *self, loff_t offs, uint32_t *data);
ssize_t smio_thsafe_client_read_64 (smio_t *self, loff_t offs, uint64_t *data);
/* Read data from device with raw address (no base address mangling) */
ssize_t smio_thsafe_raw_client_read_16 (smio_t *self, loff_t offs, uint16_t *data);
ssize_t smio_thsafe_raw_client_read_32 (smio_t *self, loff_t offs, uint32_t *data);
ssize_t smio_thsafe_raw_client_read_64 (smio_t *self, loff_t offs, uint64_t *data);
/* Write data to device */
ssize_t smio_thsafe_client_write_16 (smio_t *self, loff_t offs, const uint16_t *data);
ssize_t smio_thsafe_client_write_32 (smio_t *self, loff_t offs, const uint32_t *data);
ssize_t smio_thsafe_client_write_64 (smio_t *self, loff_t offs, const uint64_t *data);
/* Write data to device with raw address (no base address mangling) */
ssize_t smio_thsafe_raw_client_write_16 (smio_t *self, loff_t offs, const uint16_t *data);
ssize_t smio_thsafe_raw_client_write_32 (smio_t *self, loff_t offs, const uint32_t *data);
ssize_t smio_thsafe_raw_client_write_64 (smio_t *self, loff_t offs, const uint64_t *data);
/* Read data block from device, size in bytes */
ssize_t smio_thsafe_client_read_block (smio_t *self, loff_t offs, size_t size, uint32_t *data);
/* Read data block from device, size in bytes, with raw address (no base address mangling) */
ssize_t smio_thsafe_raw_client_read_block (smio_t *self, loff_t offs, size_t size, uint32_t *data);
/* Write data block from device, size in bytes */
ssize_t smio_thsafe_client_write_block (smio_t *self, loff_t offs, size_t size, const uint32_t *data);
/* Read data block via DMA from device, size in bytes */
/* Write data block from device, size in bytes, with raw address (no base address mangling) */
ssize_t smio_thsafe_raw_client_write_block (smio_t *self, loff_t offs, size_t size, const uint32_t *data);
/* read data block via dma from device, size in bytes */
ssize_t smio_thsafe_client_read_dma (smio_t *self, loff_t offs, size_t size, uint32_t *data);
/* read data block via dma from device, size in bytes, with raw address (no base address mangling) */
ssize_t smio_thsafe_raw_client_read_dma (smio_t *self, loff_t offs, size_t size, uint32_t *data);
/* Write data block via DMA from device, size in bytes */
ssize_t smio_thsafe_client_write_dma (smio_t *self, loff_t offs, size_t size, const uint32_t *data);
/* Write data block via DMA from device, size in bytes, with raw address (no base address mangling) */
ssize_t smio_thsafe_raw_client_write_dma (smio_t *self, loff_t offs, size_t size, const uint32_t *data);
/* Read device information */
/* int smio_thsafe_client_read_info (smio_t *self, llio_dev_info_t *dev_info) */
......
hal/sm_io/sm_io_bootstrap.c
View file @ 9ec11089
......@@ -42,7 +42,7 @@
#define EXTRA_SMIO_SERV_BYTES 1
static struct _smio_t *_smio_new (struct _devio_t *parent, struct _zctx_t *ctx,
void *pipe, char *broker, char *service, int verbose);
void *pipe, char *broker, char *service, uint32_t base, int verbose);
static smio_err_e _smio_destroy (struct _smio_t **self_p);
static smio_err_e _smio_loop (smio_t *self);
......@@ -61,8 +61,10 @@ void smio_startup (void *args, zctx_t *ctx, void *pipe)
/* We must export our service as the combination of the
* devio name (coming from devio parent) and our own name ID
* followed by an optional parameter coming from priv pointer */
char *smio_service = halutils_concat_strings (th_args->service,
smio_mod_dispatch[th_args->smio_id].name, ':');
char *inst_id_str = halutils_stringify_dec_key (th_args->inst_id);
ASSERT_ALLOC(inst_id_str, err_inst_id_str_alloc);
char *smio_service = halutils_concat_strings3 (th_args->service,
smio_mod_dispatch[th_args->smio_id].name, inst_id_str, ':');
ASSERT_ALLOC(smio_service, err_smio_service_alloc);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io_bootstrap] SMIO Thread %s "
......@@ -71,7 +73,7 @@ void smio_startup (void *args, zctx_t *ctx, void *pipe)
"allocating resources ...\n", smio_service);
smio_t *self = _smio_new (th_args->parent, ctx, pipe, th_args->broker,
smio_service, th_args->verbose);
smio_service, th_args->base, th_args->verbose);
ASSERT_ALLOC(self, err_self_alloc);
/* Call SMIO init function to finish initializing its internal strucutres */
......@@ -106,6 +108,8 @@ err_self_alloc:
smio_service);
free (smio_service);
err_smio_service_alloc:
free (inst_id_str);
err_inst_id_str_alloc:
free (th_args);
return;
}
......@@ -122,8 +126,10 @@ void smio_config_defaults (void *args, zctx_t *ctx, void *pipe)
/* We must export our service as the combination of the
* devio name (coming from devio parent) and our own name ID
* followed by an optional parameter coming from priv pointer */
char *smio_service = halutils_concat_strings (th_args->service,
smio_mod_dispatch[th_args->smio_id].name, ':');
char *inst_id_str = halutils_stringify_dec_key (th_args->inst_id);
ASSERT_ALLOC(inst_id_str, err_inst_id_str_alloc);
char *smio_service = halutils_concat_strings3 (th_args->service,
smio_mod_dispatch[th_args->smio_id].name, inst_id_str, ':');
ASSERT_ALLOC(smio_service, err_smio_service_alloc);
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io_bootstrap] Config Thread %s "
......@@ -138,6 +144,8 @@ void smio_config_defaults (void *args, zctx_t *ctx, void *pipe)
"exiting\n", smio_service);
free (smio_service);
err_smio_service_alloc:
free (inst_id_str);
err_inst_id_str_alloc:
free (th_args);
return;
}
......@@ -147,9 +155,9 @@ err_smio_service_alloc:
/************************************************************/
struct _smio_t *smio_new (struct _devio_t *parent, struct _zctx_t *ctx, void *pipe,
char *broker, char *service, int verbose)
char *broker, char *service, uint32_t base, int verbose)
{
return _smio_new (parent, ctx, pipe, broker, service, verbose);
return _smio_new (parent, ctx, pipe, broker, service, base, verbose);
}
smio_err_e smio_destroy (struct _smio_t **self_p)
......@@ -167,8 +175,8 @@ smio_err_e smio_loop (struct _smio_t *self)
/************************************************************/
/* Boot new sm_io instance of fmc130m_4ch */
static struct _smio_t *_smio_new (struct _devio_t *parent, struct _zctx_t *ctx, void *pipe,
char *broker, char *service, int verbose)
static struct _smio_t *_smio_new (struct _devio_t *parent, struct _zctx_t *ctx,
void *pipe, char *broker, char *service, uint32_t base, int verbose)
{
(void) parent;
......@@ -188,6 +196,9 @@ static struct _smio_t *_smio_new (struct _devio_t *parent, struct _zctx_t *ctx,
self->ctx = ctx;
self->pipe = pipe;
/* Initialize SMIO base address */
self->base = base;
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io_bootstrap] Creating worker\n");
DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "\tbroker = %s, service = %s, verbose = %d\n",
broker, service, verbose);
......
hal/sm_io/sm_io_bootstrap.h
View file @ 9ec11089
......@@ -67,8 +67,8 @@ struct _th_boot_args_t {
char *broker; /* Endpoint to connect to broker */
char *service; /* (part of) the service name to be exported */
int verbose; /* Print trace information to stdout*/
void *priv; /* Pointer to a private strucutre to be passed
untouched by devio to the specific smio instace*/
uint32_t base; /* SMIO base address */
uint32_t inst_id; /* SMIO instance ID */
};
typedef struct _th_boot_args_t th_boot_args_t;
......@@ -76,6 +76,7 @@ typedef struct _th_boot_args_t th_boot_args_t;
/* Config thread args structure */
struct _th_config_args_t {
uint32_t smio_id; /* ID of the SMIO instance */
uint32_t inst_id; /* SMIO instance ID */
char *broker; /* Endpoint to connect to broker */
char *service; /* Full name of the exported service */
char *log_file; /* Thread log file */
......@@ -88,8 +89,8 @@ typedef struct _th_config_args_t th_config_args_t;
/************************************************************/
void smio_startup (void *args, zctx_t *ctx, void *pipe);
void smio_config_defaults (void *args, zctx_t *ctx, void *pipe);
struct _smio_t *smio_new (struct _devio_t *parent, struct _zctx_t *ctx, void *pipe,
char *broker, char *service, int verbose);
struct _smio_t *smio_new (struct _devio_t *parent, struct _zctx_t *ctx,
void *pipe, char *broker, char *service, uint32_t base, int verbose);
smio_err_e smio_destroy (struct _smio_t **self_p);
smio_err_e smio_loop (struct _smio_t *self);
......
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