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bpm-sw
Commit 30da56f6 authored by Lucas Russo's avatar Lucas Russo
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ll_io/*/*pcie.c: add PCIe software reset 

For now, we reset the FPGA on PCIe open.
parent 7857974a
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src/ll_io/ops/ll_io_pcie.c
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......@@ -67,6 +67,7 @@ static ssize_t _pcie_rw_bar4_block_raw (llio_t *self, uint32_t pg_start, uint64_
static ssize_t _pcie_rw_block (llio_t *self, uint64_t offs, size_t size,
uint32_t *data, int rw);
static ssize_t _pcie_timeout_reset (llio_t *self);
static ssize_t _pcie_reset_fpga (llio_t *self);
/************ Our methods implementation **********/
......@@ -179,13 +180,18 @@ static int pcie_open (llio_t *self, llio_endpoint_t *endpoint)
SET_SDRAM_PG(dev_pcie->bar0, 0);
SET_WB_PG(dev_pcie->bar0, 0);
/* Attach this PCIe device to LLIO instance */
llio_set_dev_handler (self, dev_pcie);
/* Signal that the endpoint is opened and ready to work */
llio_set_endpoint_open (self, true);
DBE_DEBUG (DBG_LL_IO | DBG_LVL_INFO,
"[ll_io_pcie] Opened PCIe device located at %s\n",
llio_get_endpoint_name (self));
/* Reset FPGA */
_pcie_reset_fpga (self);
return err;
err_dev_handler_alloc:
......@@ -631,6 +637,16 @@ static ssize_t _pcie_timeout_reset (llio_t *self)
return _pcie_rw_32 (self, offs, &data, WRITE_TO_BAR);
}
static ssize_t _pcie_reset_fpga (llio_t *self)
{
DBE_DEBUG (DBG_LL_IO | DBG_LVL_TRACE,
"[ll_io_pcie:_pcie_reset_fpga] Reseting FPGA\n");
uint64_t offs = BAR0_ADDR | PCIE_CFG_REG_EB_STACON;
uint32_t data = PCIE_CFG_TX_CTRL_CHANNEL_RST;
return _pcie_rw_32 (self, offs, &data, WRITE_TO_BAR);
}
const llio_ops_t llio_ops_pcie = {
.open = pcie_open, /* Open device */
.release = pcie_release, /* Release device */
......
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