hdl/top/afc_v3/vivado/*/*.xdc: add new delta-sigma CE constraint

Now, we only have one delta-sigma component instantiation at the FOFB
rate, working iterativelly with one clock cycle per input bit. So, we
need a total of 32 clock cycles, corresponding to 32 input bits.

The FOFB decimation rate is 980, so we could have a CE up to 980/32
and still produce correct results. However, in order to minimize latency
we use the minimum CE avaiable to give an extra timing margin and
still reduce latency. In our case, this value is 2, the ADC CE.