testbench/*/wb_acq_core_tb/*: add minimum wait time before valid data cycle

This is needed for the new wb_facq_core. If we are using a larger bus than the internal one (128-bit) we need to assert the valid cycle for that data accordingly. For instance, if we are using 256-bit and the internal wb_acq_core bus is 128, we need to assert the valid bit at a maximum rate of 0.5, meaning 1 valid clock cycle for a minimum of 2 cycles. This is because the internal word packer does not have a FIFO and so it needs the amount a minimum number of clock cycles to transfer all of the data words.

testbench//wb_acq_core_tb/: add minimum wait time before valid data cycle
This is needed for the new wb_facq_core. If we are using a larger bus than the internal one (128-bit) we need to assert the valid cycle for that data accordingly. For instance, if we are using 256-bit and the internal wb_acq_core bus is 128, we need to assert the valid bit at a maximum rate of 0.5, meaning 1 valid clock cycle for a minimum of 2 cycles. This is because the internal word packer does not have a FIFO and so it needs the amount a minimum number of clock cycles to transfer all of the data words.
dc8e0624 · Lucas Russo · e9d2ad2a · dc8e0624
Commit dc8e0624 authored Jul 25, 2016 by Lucas Russo
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Showing with 26 additions and 6 deletions

wb_acq_core_tb.v ...acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v +26 -6

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--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v
@@ -1604,6 +1604,9 @@ module wb_acq_core_tb;
    // Default values. 200 ADC CLK cycles after star wait
    min_wait_trig = 200;
    max_wait_trig = 200;
+    // Initial values for f_gen_bit_one
+    f_gen_bit_one.wait_cycles = 0;
+    f_gen_bit_one.gen_valid = 0;

    $display("-----------------------------------");
    $display("@%0d: Simulation of BPM ACQ FSM starting!", $time);
@@ -2326,7 +2329,7 @@ module wb_acq_core_tb;
        data_test_0 <= data_test_0 + 1;
      end

-      data_test_dvalid_t[0] <= f_gen_data_rdy_gen(data_valid_threshold);
+      data_test_dvalid_t[0] <= f_gen_data_rdy_gen(data_valid_threshold, 1);
      data_test_dvalid[0] <= data_test_dvalid_t[0];
      data_test_trig[0] <= data_trig;
    end else begin
@@ -2355,7 +2358,7 @@ module wb_acq_core_tb;
            data_test[ch] <= data_test[ch] + ch + 1;
          end

-          data_test_dvalid_t[ch] <= f_gen_data_rdy_gen(data_valid_threshold);
+          data_test_dvalid_t[ch] <= f_gen_data_rdy_gen(data_valid_threshold, 1);
          data_test_dvalid[ch] <= data_test_dvalid_t[ch];
          data_test_trig[ch] <= data_trig;
        end else begin
@@ -2382,9 +2385,10 @@ module wb_acq_core_tb;

  function f_gen_data_rdy_gen;
    input real prob;
+    input integer min_wait_cycles;
    real temp;
  begin
-    f_gen_data_rdy_gen = f_gen_bit_one(prob);
+    f_gen_data_rdy_gen = f_gen_bit_one(prob, min_wait_cycles);
  end
  endfunction

@@ -2392,21 +2396,37 @@ module wb_acq_core_tb;
    input real prob;
    real temp;
  begin
-    f_gen_data_stall = f_gen_bit_one(1.0-prob);
+    f_gen_data_stall = f_gen_bit_one(1.0-prob, 0);
  end
  endfunction

  function f_gen_bit_one;
    input real prob;
+    input integer min_wait_cycles;
    real temp;
+    integer wait_cycles;
+    integer gen_valid;
  begin
+
+   // count wait_cycles up to min_wait_cycles
+   if (wait_cycles >= min_wait_cycles) begin
+     gen_valid = 1;
+     wait_cycles = 0;
+   end else begin
+     gen_valid = 0;
+     wait_cycles = wait_cycles + 1;
+   end
+
    // $random is surronded by the concat operator in order
    // to provide us with only unsigned (bit vector) data.
    // Generates valud in a 0..1 range
    temp = ({$random} % 100 + 1)/100.00;//threshold;

-    if (temp <= prob)
-     f_gen_bit_one = 1'b1;
+    if (gen_valid == 1)
+      if (temp <= prob)
+       f_gen_bit_one = 1'b1;
+      else
+        f_gen_bit_one = 1'b0;
    else
      f_gen_bit_one = 1'b0;
  end