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Lucas Russo authored
This is needed for the new wb_facq_core. If we are using a larger bus than the internal one (128-bit) we need to assert the valid cycle for that data accordingly. For instance, if we are using 256-bit and the internal wb_acq_core bus is 128, we need to assert the valid bit at a maximum rate of 0.5, meaning 1 valid clock cycle for a minimum of 2 cycles. This is because the internal word packer does not have a FIFO and so it needs the amount a minimum number of clock cycles to transfer all of the data words.
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