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wr-switch-hdl
Commit 3abab680 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_softpll_ng: cleaned up, added comments

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modules/softpll-new/wr_softpll_ng.vhd
View file @ 3abab680
-------------------------------------------------------------------------------
-- Title : White Rabbit Softcore PLL (new generation) - SoftPLL-ng
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : wr_softpll_ng.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2012-03-26
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- The hardware part of the revised softcore PLL. Incorporates a user-defined
-- number of DDMTD taggers, a FIFO allowing for sequential readout of
-- the phase tags and ports for driving oscillator tuning DACs.
-- The rest of the magic is done in the software.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......@@ -8,13 +48,31 @@ use work.spll_wbgen2_pkg.all;
entity wr_softpll_ng is
generic(
-- Number of bits in phase tags produced by DDMTDs.
-- Must be large enough to cover at least a hundred of DDMTD periods to ensure
-- correct operation of the SoftPLL software servo algorithm - that
-- means, for a typical DMTD frequency offset N=16384, there number of tag bits
-- should be log2(N) + 7 == 21. Note: the value must match the TAG_BITS constant
-- in spll_defs.h file!
g_tag_bits : integer;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE;
-- These two are obvious:
g_num_ref_inputs : integer := 1;
g_num_outputs : integer := 1;
g_with_period_detector: boolean := false
-- When true, an additional period detector is provided, measuring the
-- frequency offset between the DDMTD clock and a chosen reference input clock.
-- The feature is not required by the current version of the SoftPLL servo
-- algorithm, but is kept for testing/debugging purposes.
g_with_period_detector : boolean := false;
-- When true, an additional FIFO is instantiated, providing a realtime record
-- of user-selectable SoftPLL parameters (e.g. tag values, phase error, DAC drive).
-- These values can be read by "spll_dbg_proxy" daemon for further analysis.
g_with_debug_fifo : boolean := false;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
......@@ -23,23 +81,31 @@ entity wr_softpll_ng is
-- Reference inputs (i.e. the RX clocks recovered by the PHYs)
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
-- Feedback clocks (i.e. the outputs of the main or aux oscillator)
-- Feedback clocks (i.e. the outputs of the main or auxillary oscillator)
-- Note: clk_fb_i(0) must be always connected to the primary board's oscillator
-- (i.e. the one driving the PTP and Ethernet PHY) to ensure correct operation
-- of the PTP core.
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
-- DMTD Offset clock
clk_dmtd_i : in std_logic;
-- DMTD oscillator drive
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
-- When HI, load the data from dac_dmtd_data_o to the DAC.
dac_dmtd_load_o : out std_logic;
-- Output channel DAC value
dac_out_data_o : out std_logic_vector(15 downto 0);
-- Output channel select (0 = channel 0, etc. )
-- Output channel select (0 = Output channel 0, 1 == OC 1, etc...)
dac_out_sel_o : out std_logic_vector(3 downto 0);
dac_out_load_o : out std_logic;
-- Output enable input: when HI, enables locking the output(s)
-- to the reference clock(s)
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
-- When HI, the respective clock output is locked.
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
wb_adr_i : in std_logic_vector(6 downto 0);
......@@ -53,6 +119,8 @@ entity wr_softpll_ng is
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(3 downto 0);
-- Debug FIFO readout interrupt
dbg_fifo_irq_o : out std_logic
);
......@@ -396,9 +464,9 @@ begin -- rtl
wb_irq_o <= wb_irq_out;
gen_with_period_detector: if(g_with_period_detector) generate
gen_with_period_detector : if(g_with_period_detector) generate
per_clk_ref(g_num_ref_inputs-1 downto 0) <= clk_ref_i;-- and g_period_detector_ref_mask(g_num_ref_inputs-1 downto 0);
per_clk_ref(g_num_ref_inputs-1 downto 0) <= clk_ref_i; -- and g_period_detector_ref_mask(g_num_ref_inputs-1 downto 0);
per_clk_ref(g_num_ref_inputs) <= clk_fb_i(0);
-- Frequency/Period detector (to speed up locking)
......@@ -440,7 +508,7 @@ begin -- rtl
end generate gen_with_period_detector;
gen_without_period_detector: if(g_with_period_detector = false) generate
gen_without_period_detector : if(g_with_period_detector = false) generate
regs_out.per_hpll_valid_i <= '0';
end generate gen_without_period_detector;
......@@ -570,6 +638,8 @@ begin -- rtl
-- Debugging FIFO
-----------------------------------------------------------------------------
gen_with_debug_fifo : if(g_with_debug_fifo = true) generate
dbg_fifo_almostfull <= '1' when unsigned(regs_in.dfr_host_wr_usedw_o) > 8180 else '0';
p_request_counter : process(clk_sys_i)
......@@ -619,6 +689,12 @@ begin -- rtl
regs_out.dfr_host_value_i <= regs_in.dfr_spll_eos_o & regs_in.dfr_spll_value_o;
regs_out.dfr_host_seq_id_i <= std_logic_vector(dbg_seq_id);
end generate gen_with_debug_fifo;
gen_without_debug_fifo: if(g_with_debug_fifo = false) generate
regs_out.dfr_host_wr_req_i <= '0';
end generate gen_without_debug_fifo;
-----------------------------------------------------------------------------
-- CSR N_OUT/N_REF fields
-----------------------------------------------------------------------------
......
modules/softpll-new/xwr_softpll_ng.vhd
View file @ 3abab680
-------------------------------------------------------------------------------
-- Title : White Rabbit Softcore PLL (new generation) - SoftPLL-ng
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : xwr_softpll_ng.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2012-03-26
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- Struct'ized version of wr_softpll_ng.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity xwr_softpll_ng is
generic(
-- Number of bits in phase tags produced by DDMTDs.
-- Must be large enough to cover at least a hundred of DDMTD periods to ensure
-- correct operation of the SoftPLL software servo algorithm - that
-- means, for a typical DMTD frequency offset N=16384, there number of tag bits
-- should be log2(N) + 7 == 21. Note: the value must match the TAG_BITS constant
-- in spll_defs.h file!
g_tag_bits : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ref_inputs : integer;
g_num_outputs : integer;
g_period_detector_ref_mask : std_logic_vector(31 downto 0) := x"ffffffff"
-- These two are obvious:
g_num_ref_inputs : integer := 1;
g_num_outputs : integer := 1;
-- When true, an additional period detector is provided, measuring the
-- frequency offset between the DDMTD clock and a chosen reference input clock.
-- The feature is not required by the current version of the SoftPLL servo
-- algorithm, but is kept for testing/debugging purposes.
g_with_period_detector : boolean := false;
-- When true, an additional FIFO is instantiated, providing a realtime record
-- of user-selectable SoftPLL parameters (e.g. tag values, phase error, DAC drive).
-- These values can be read by "spll_dbg_proxy" daemon for further analysis.
g_with_debug_fifo : boolean := false;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
......@@ -43,21 +98,23 @@ entity xwr_softpll_ng is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
debug_o : out std_logic_vector(3 downto 0)
debug_o : out std_logic_vector(3 downto 0);
dbg_fifo_irq_o : out std_logic
);
end xwr_softpll_ng;
architecture wrapper of xwr_softpll_ng is
component wr_softpll_ng
generic (
g_tag_bits : integer;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_ref_inputs : integer;
g_num_outputs : integer--;
-- g_period_detector_ref_mask : std_logic_vector(31 downto 0) := x"ffffffff"
);
g_num_outputs : integer;
g_with_period_detector : boolean;
g_with_debug_fifo : boolean;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -81,7 +138,8 @@ architecture wrapper of xwr_softpll_ng is
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(3 downto 0));
debug_o : out std_logic_vector(3 downto 0);
dbg_fifo_irq_o : out std_logic);
end component;
begin -- behavioral
......@@ -92,8 +150,9 @@ begin -- behavioral
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_num_ref_inputs => g_num_ref_inputs,
g_num_outputs => g_num_outputs)
-- g_period_detector_ref_mask => g_period_detector_ref_mask)
g_num_outputs => g_num_outputs,
g_with_debug_fifo => g_with_debug_fifo,
g_with_period_detector => g_with_period_detector)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......@@ -117,6 +176,7 @@ begin -- behavioral
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
wb_irq_o => slave_o.int,
debug_o => debug_o);
debug_o => debug_o,
dbg_fifo_irq_o => dbg_fifo_irq_o);
end wrapper;
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