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wr-switch-hdl
Commit 358ff7a5 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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swcore: beautifulized i/o block sources

parent a41240fb
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modules/wrsw_swcore/xswc_input_block.vhd
View file @ 358ff7a5
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski -- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT -- Company : CERN BE-Co-HT
-- Created : 2010-10-28 -- Created : 2010-10-28
-- Last update: 2012-03-09 -- Last update: 2012-03-15
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'87 -- Standard : VHDL'87
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -226,7 +226,7 @@ entity xswc_input_block is ...@@ -226,7 +226,7 @@ entity xswc_input_block is
pta_prio_o : out std_logic_vector(g_prio_width - 1 downto 0); pta_prio_o : out std_logic_vector(g_prio_width - 1 downto 0);
tap_out_o: out std_logic_vector(49 + 62 downto 0) tap_out_o : out std_logic_vector(49 + 62 downto 0)
); );
end xswc_input_block; end xswc_input_block;
...@@ -540,7 +540,7 @@ architecture syn of xswc_input_block is ...@@ -540,7 +540,7 @@ architecture syn of xswc_input_block is
return tmp; return tmp;
end f_gen_mask; end f_gen_mask;
function f_slv_resize(x: std_logic_vector; len: natural) return std_logic_vector is function f_slv_resize(x : std_logic_vector; len : natural) return std_logic_vector is
variable tmp : std_logic_vector(len-1 downto 0); variable tmp : std_logic_vector(len-1 downto 0);
begin begin
tmp := (others => '0'); tmp := (others => '0');
...@@ -551,42 +551,42 @@ architecture syn of xswc_input_block is ...@@ -551,42 +551,42 @@ architecture syn of xswc_input_block is
function f_enum2nat (enum_arg :t_page_alloc) return std_logic_vector is function f_enum2nat (enum_arg : t_page_alloc) return std_logic_vector is
begin begin
for t in t_page_alloc loop for t in t_page_alloc loop
if(enum_arg = t) then if(enum_arg = t) then
return std_logic_vector(to_unsigned(t_page_alloc'pos(t),4)); return std_logic_vector(to_unsigned(t_page_alloc'pos(t), 4));
end if; end if;
end loop; -- i end loop; -- i
return "0000"; return "0000";
end function f_enum2nat; end function f_enum2nat;
function f_enum2nat (enum_arg :t_rcv_pck) return std_logic_vector is function f_enum2nat (enum_arg : t_rcv_pck) return std_logic_vector is
begin begin
for t in t_rcv_pck loop for t in t_rcv_pck loop
if(enum_arg = t) then if(enum_arg = t) then
return std_logic_vector(to_unsigned(t_rcv_pck'pos(t),4)); return std_logic_vector(to_unsigned(t_rcv_pck'pos(t), 4));
end if; end if;
end loop; -- i end loop; -- i
return "0000"; return "0000";
end function f_enum2nat; end function f_enum2nat;
function f_enum2nat (enum_arg :t_ll_write) return std_logic_vector is function f_enum2nat (enum_arg : t_ll_write) return std_logic_vector is
begin begin
for t in t_ll_write loop for t in t_ll_write loop
if(enum_arg = t) then if(enum_arg = t) then
return std_logic_vector(to_unsigned(t_ll_write'pos(t),4)); return std_logic_vector(to_unsigned(t_ll_write'pos(t), 4));
end if; end if;
end loop; -- i end loop; -- i
return "0000"; return "0000";
end function f_enum2nat; end function f_enum2nat;
function f_enum2nat (enum_arg :t_transfer_pck) return std_logic_vector is function f_enum2nat (enum_arg : t_transfer_pck) return std_logic_vector is
begin begin
for t in t_transfer_pck loop for t in t_transfer_pck loop
if(enum_arg = t) then if(enum_arg = t) then
return std_logic_vector(to_unsigned(t_transfer_pck'pos(t),4)); return std_logic_vector(to_unsigned(t_transfer_pck'pos(t), 4));
end if; end if;
end loop; -- i end loop; -- i
return "0000"; return "0000";
end function f_enum2nat; end function f_enum2nat;
......
modules/wrsw_swcore/xswc_output_block.vhd
View file @ 358ff7a5
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski -- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT -- Company : CERN BE-Co-HT
-- Created : 2010-11-03 -- Created : 2010-11-03
-- Last update: 2012-02-16 -- Last update: 2012-03-15
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'87 -- Standard : VHDL'87
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -61,18 +61,18 @@ use work.ep_wbgen2_pkg.all; -- tom ...@@ -61,18 +61,18 @@ use work.ep_wbgen2_pkg.all; -- tom
entity xswc_output_block is entity xswc_output_block is
generic ( generic (
g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width g_max_pck_size_width : integer; --:= c_swc_max_pck_size_width
g_output_block_per_prio_fifo_size : integer ;--:= c_swc_output_fifo_size g_output_block_per_prio_fifo_size : integer; --:= c_swc_output_fifo_size
g_prio_width : integer ;--:= c_swc_prio_width;, c_swc_output_prio_num_width g_prio_width : integer; --:= c_swc_prio_width;, c_swc_output_prio_num_width
g_prio_num : integer ;--:= c_swc_output_prio_num g_prio_num : integer; --:= c_swc_output_prio_num
-- new stuff -- new stuff
g_mpm_page_addr_width : integer ;--:= c_swc_page_addr_width; g_mpm_page_addr_width : integer; --:= c_swc_page_addr_width;
g_mpm_data_width : integer ;--:= c_swc_page_addr_width; g_mpm_data_width : integer; --:= c_swc_page_addr_width;
g_mpm_partial_select_width : integer ; g_mpm_partial_select_width : integer;
g_mpm_fetch_next_pg_in_advance : boolean := false; g_mpm_fetch_next_pg_in_advance : boolean := false;
g_wb_data_width : integer ; g_wb_data_width : integer;
g_wb_addr_width : integer ; g_wb_addr_width : integer;
g_wb_sel_width : integer ; g_wb_sel_width : integer;
g_wb_ob_ignore_ack : boolean := true g_wb_ob_ignore_ack : boolean := true
); );
port ( port (
...@@ -209,7 +209,7 @@ architecture behavoural of xswc_output_block is ...@@ -209,7 +209,7 @@ architecture behavoural of xswc_output_block is
signal src_rty_int : std_logic; signal src_rty_int : std_logic;
signal mpm_pg_addr_memorized : std_logic_vector(g_mpm_page_addr_width -1 downto 0); signal mpm_pg_addr_memorized : std_logic_vector(g_mpm_page_addr_width -1 downto 0);
signal mpm_pg_addr_memorized_valid: std_logic; signal mpm_pg_addr_memorized_valid : std_logic;
signal mpm_dreq : std_logic; signal mpm_dreq : std_logic;
signal mpm_abort : std_logic; signal mpm_abort : std_logic;
...@@ -231,9 +231,9 @@ architecture behavoural of xswc_output_block is ...@@ -231,9 +231,9 @@ architecture behavoural of xswc_output_block is
signal not_set_next_pg_addr : std_logic; signal not_set_next_pg_addr : std_logic;
begin -- behavoural begin -- behavoural
zeros <=(others => '0'); zeros <= (others => '0');
ram_zeros <=(others => '0'); ram_zeros <= (others => '0');
ram_ones <=(others => '1'); ram_ones <= (others => '1');
wr_prio <= not pta_prio_i; wr_prio <= not pta_prio_i;
...@@ -289,7 +289,7 @@ begin -- behavoural ...@@ -289,7 +289,7 @@ begin -- behavoural
"00100000" when wr_prio = "101" else "00100000" when wr_prio = "101" else
"01000000" when wr_prio = "110" else "01000000" when wr_prio = "110" else
"10000000" when wr_prio = "111" else "10000000" when wr_prio = "111" else
"00000000" ; "00000000";
wr_en <= write(0) and not_full_array(0) when wr_prio = "000" else wr_en <= write(0) and not_full_array(0) when wr_prio = "000" else
write(1) and not_full_array(1) when wr_prio = "001" else write(1) and not_full_array(1) when wr_prio = "001" else
...@@ -313,7 +313,7 @@ begin -- behavoural ...@@ -313,7 +313,7 @@ begin -- behavoural
prio_ctrl : for i in 0 to g_prio_num - 1 generate prio_ctrl : for i in 0 to g_prio_num - 1 generate
write(i) <= write_array(i) and pta_transfer_data_valid_i ; write(i) <= write_array(i) and pta_transfer_data_valid_i;
read(i) <= read_array(i) and mpm_pg_valid; read(i) <= read_array(i) and mpm_pg_valid;
-- drop_imp: -- drop_imp:
-- read(i) <= (read_array(i) and mpm_pg_valid) or (drop_array(i) and not mpm_pg_valid); -- read(i) <= (read_array(i) and mpm_pg_valid) or (drop_array(i) and not mpm_pg_valid);
...@@ -532,14 +532,14 @@ begin -- behavoural ...@@ -532,14 +532,14 @@ begin -- behavoural
end if; end if;
end process p_prep_to_send_fsm; end process p_prep_to_send_fsm;
next_page_set_in_advance: if (g_mpm_fetch_next_pg_in_advance = TRUE) generate next_page_set_in_advance : if (g_mpm_fetch_next_pg_in_advance = true) generate
set_next_pg_addr <= '1' when (rd_data_valid = '1' and mpm_pg_req_i = '1' and mpm_pg_valid = '0') else '0'; set_next_pg_addr <= '1' when (rd_data_valid = '1' and mpm_pg_req_i = '1' and mpm_pg_valid = '0') else '0';
not_set_next_pg_addr <= '1' when (rd_data_valid = '0' and mpm_pg_req_i = '1') else '0'; not_set_next_pg_addr <= '1' when (rd_data_valid = '0' and mpm_pg_req_i = '1') else '0';
end generate next_page_set_in_advance; end generate next_page_set_in_advance;
next_page_set_after_pck_transmision: if (g_mpm_fetch_next_pg_in_advance = FALSE) generate next_page_set_after_pck_transmision : if (g_mpm_fetch_next_pg_in_advance = false) generate
set_next_pg_addr <= '1' when (rd_data_valid = '1' and mpm_pg_req_i = '1' and mpm_pg_valid = '0' and s_send_pck = S_IDLE) else '0'; set_next_pg_addr <= '1' when (rd_data_valid = '1' and mpm_pg_req_i = '1' and mpm_pg_valid = '0' and s_send_pck = S_IDLE) else '0';
not_set_next_pg_addr <= '1' when (mpm_pg_req_i = '1' and mpm_pg_valid = '0' ) else '0'; not_set_next_pg_addr <= '1' when (mpm_pg_req_i = '1' and mpm_pg_valid = '0') else '0';
end generate next_page_set_after_pck_transmision; end generate next_page_set_after_pck_transmision;
...@@ -567,10 +567,10 @@ begin -- behavoural ...@@ -567,10 +567,10 @@ begin -- behavoural
src_out_int.cyc <= '0'; src_out_int.cyc <= '0';
src_out_int.sel <= (others => '0'); src_out_int.sel <= (others => '0');
start_free_pck <= '0'; start_free_pck <= '0';
start_free_pck_addr <= (others =>'0'); start_free_pck_addr <= (others => '0');
tmp_adr <= (others =>'0'); tmp_adr <= (others => '0');
tmp_dat <= (others =>'0'); tmp_dat <= (others => '0');
tmp_sel <= (others =>'0'); tmp_sel <= (others => '0');
--======================================== --========================================
else else
-- default values -- default values
...@@ -731,7 +731,7 @@ begin -- behavoural ...@@ -731,7 +731,7 @@ begin -- behavoural
-- ppfm_free <= '1'; -- ppfm_free <= '1';
-- ppfm_free_pgaddr <= rd_data(g_mpm_page_addr_width - 1 downto 0); -- ppfm_free_pgaddr <= rd_data(g_mpm_page_addr_width - 1 downto 0);
elsif(ppfm_free_done_i = '1') then elsif(ppfm_free_done_i = '1') then
ppfm_free <='0'; ppfm_free <= '0';
ppfm_free_pgaddr <= (others => '0'); ppfm_free_pgaddr <= (others => '0');
end if; end if;
end if; end if;
...@@ -752,7 +752,7 @@ begin -- behavoural ...@@ -752,7 +752,7 @@ begin -- behavoural
'0'; '0';
mpm2wb_adr_int <= mpm_d_i(g_mpm_data_width -1 downto g_mpm_data_width - g_wb_addr_width); mpm2wb_adr_int <= mpm_d_i(g_mpm_data_width -1 downto g_mpm_data_width - g_wb_addr_width);
mpm2wb_sel_int <= '1' & mpm_dsel_i ; -- TODO: something generic mpm2wb_sel_int <= '1' & mpm_dsel_i; -- TODO: something generic
mpm2wb_dat_int <= mpm_d_i(g_wb_data_width -1 downto 0); mpm2wb_dat_int <= mpm_d_i(g_wb_data_width -1 downto 0);
-- source out -- source out
......
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