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white-rabbit
wr-nic
Commits
8ccbd8b8
Commit
8ccbd8b8
authored
Jul 05, 2012
by
Javier Díaz
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Plain Diff
Code cleaning
parent
7921a99c
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4 changed files
with
156 additions
and
138 deletions
+156
-138
wrsw_dio.vhd
modules/wrsw_dio/wrsw_dio.vhd
+35
-35
wr_nic.xise
syn/spec/wr_nic.xise
+2
-2
wr_nic_top.ucf
top/spec/wr_nic_top.ucf
+5
-5
wr_nic_top.vhd
top/spec/wr_nic_top.vhd
+114
-96
No files found.
modules/wrsw_dio/wrsw_dio.vhd
View file @
8ccbd8b8
...
...
@@ -3,7 +3,7 @@
-- Project : White Rabbit Network Interface
-------------------------------------------------------------------------------
-- File : wrsw_dio.vhd
-- Author : Rafael Rodriguez
-- Author : Rafael Rodriguez
, Javier Díaz
-- Company : Seven Solutions
-- Created : 2012-03-03
-- Last update: 2012-03-20
...
...
@@ -23,6 +23,7 @@
-- Date Version Author Description
-- 2012-03-03 0.1 Rafa.r Created
-- 2012-03-08 0.2 Javier.d Added wrsw_dio_wb
-- 2012-07-05 0.3 Javier.d Midified wrsw_dio_wb, modified interface
-------------------------------------------------------------------------------
-- WARNING: only pipelined mode is supported (Intercon is pipelined only) - T.W.
...
...
@@ -56,13 +57,15 @@ entity wrsw_dio is
dio_led_top_o
:
out
std_logic
;
dio_led_bot_o
:
out
std_logic
;
fmc_scl_b
:
inout
std_logic
;
fmc_sda_b
:
inout
std_logic
;
dio_scl_b
:
inout
std_logic
;
dio_sda_b
:
inout
std_logic
;
dio_ga_o
:
out
std_logic_vector
(
1
downto
0
);
tm_time_valid_i
:
in
std_logic
;
tm_seconds_i
:
in
std_logic_vector
(
39
downto
0
);
tm_cycles_i
:
in
std_logic_vector
(
27
downto
0
);
-- Debug signals for chipscope
TRIG0
:
out
std_logic_vector
(
31
downto
0
);
TRIG1
:
out
std_logic_vector
(
31
downto
0
);
TRIG2
:
out
std_logic_vector
(
31
downto
0
);
...
...
@@ -70,7 +73,7 @@ entity wrsw_dio is
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
-- wb_irq_data_fifo_o : out std_logic
-- wb_irq_data_fifo_o : out std_logic
-- T.B.DELETED
);
end
wrsw_dio
;
...
...
@@ -349,7 +352,7 @@ architecture rtl of wrsw_dio is
signal
cbar_master_in
:
t_wishbone_master_in_array
(
c_WB_SLAVES_DIO
-1
downto
0
);
signal
cbar_master_out
:
t_wishbone_master_out_array
(
c_WB_SLAVES_DIO
-1
downto
0
);
-- DIO related signa
s
ls
-- DIO related signals
signal
dio_monost
:
std_logic_vector
(
4
downto
0
);
signal
dio_prog
:
std_logic_vector
(
4
downto
0
);
signal
dio_puls_inmed
:
std_logic_vector
(
4
downto
0
);
...
...
@@ -459,12 +462,12 @@ begin
sda_padoen_o
=>
sda_pad_oen
);
fmc_scl_b
<=
scl_pad_out
when
scl_pad_oen
=
'0'
else
'Z'
;
fmc_sda_b
<=
sda_pad_out
when
sda_pad_oen
=
'0'
else
'Z'
;
scl_pad_in
<=
fmc_scl_b
;
sda_pad_in
<=
fmc_sda_b
;
dio_scl_b
<=
scl_pad_out
when
scl_pad_oen
=
'0'
else
'Z'
;
dio_sda_b
<=
sda_pad_out
when
sda_pad_oen
=
'0'
else
'Z'
;
scl_pad_in
<=
dio_scl_b
;
sda_pad_in
<=
dio_sda_b
;
dio_ga_o
<=
"00"
;
-- Innused because SPEC boards have these fmc signals to ground
------------------------------------------------------------------------------
-- WB GPIO PORT
...
...
@@ -525,7 +528,6 @@ begin
dio_sdn_ck_n_o
<=
gpio_out
(
30
);
dio_sdn_n_o
<=
gpio_out
(
31
);
--gpio_in(30) <= prsnt_m2c_l;
------------------------------------------------------------------------------
-- WB seconds-BASED PULSE GENERATION & INPUT STAMPING
------------------------------------------------------------------------------
...
...
@@ -533,7 +535,7 @@ begin
port
map
(
rst_n_i
=>
rst_n_i
,
clk_sys_i
=>
clk_sys_i
,
wb_adr_i
=>
cbar_master_out
(
3
)
.
adr
(
7
downto
2
),
wb_adr_i
=>
cbar_master_out
(
3
)
.
adr
(
7
downto
2
),
-- only word acesses are available
wb_dat_i
=>
cbar_master_out
(
3
)
.
dat
,
wb_dat_o
=>
cbar_master_in
(
3
)
.
dat
,
wb_cyc_i
=>
cbar_master_out
(
3
)
.
cyc
,
...
...
@@ -622,20 +624,6 @@ begin
dio_puls_inmed_pul_inm_4_o
=>
dio_puls_inmed
(
4
)
);
-----------------------------------------------------------------------------------
------ signals for debugging
-----------------------------------------------------------------------------------
-- TRIG0 <= tag_utc(0)(31 downto 0);
-- TRIG1(27 downto 0) <= tag_cycles(0)(27 downto 0);
-- TRIG1(0) <= cbar_master_in(3).int;
-- TRIG2 <= tm_utc(31 downto 0);
-- TRIG3(2 downto 0) <= dio_in_i(0) & dio_out(0) & dio_puls_inmed(0);
--TRIG3(4 downto 0) <= dio_tsf_wr_req(0) & tag_valid_p1(0) & gpio_out(1) & dio_in_i(0) & dio_out(0);
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
-- seconds timestamped FIFO-no-empty interrupts
irq_fifos
:
for
i
in
0
to
4
generate
irq_nempty
(
i
)
<=
not
dio_tsf_wr_empty
(
i
);
...
...
@@ -660,6 +648,18 @@ begin
end
process
;
end
generate
irq_fifos
;
-----------------------------------------------------------------------------------
------ signals for debugging
-----------------------------------------------------------------------------------
-- TRIG0 <= tag_utc(0)(31 downto 0);
-- TRIG1(27 downto 0) <= tag_cycles(0)(27 downto 0);
-- TRIG1(0) <= cbar_master_in(3).int;
-- TRIG2 <= tm_utc(31 downto 0);
-- TRIG3(2 downto 0) <= dio_in_i(0) & dio_out(0) & dio_puls_inmed(0);
--TRIG3(4 downto 0) <= dio_tsf_wr_req(0) & tag_valid_p1(0) & gpio_out(1) & dio_in_i(0) & dio_out(0);
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
end
rtl
;
...
...
syn/spec/wr_nic.xise
View file @
8ccbd8b8
...
...
@@ -326,8 +326,8 @@
<property
xil_pn:name=
"PROP_PostSynthSimTop"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_PostXlateSimTop"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_PreSynthesis"
xil_pn:value=
"PreSynthesis"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_intProjectCreationTimestamp"
xil_pn:value=
"2012-0
6-27T14:56:56
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intWbtProjectID"
xil_pn:value=
"
0F491C2760B8465F44A6DBFF4D0E0B9A
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intProjectCreationTimestamp"
xil_pn:value=
"2012-0
7-05T16:22:37
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intWbtProjectID"
xil_pn:value=
"
5349AF291E85BD2E4DF8EC38A1D830A0
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intWorkingDirLocWRTProjDir"
xil_pn:value=
"Same"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intWorkingDirUsed"
xil_pn:value=
"No"
xil_pn:valueState=
"non-default"
/>
</properties>
...
...
top/spec/wr_nic_top.ucf
View file @
8ccbd8b8
...
...
@@ -20,7 +20,7 @@ NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_cs2_n_o" LOC = B3;
NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC =
F7
;
#NET "dac_clr_n_o" LOC =
XX
;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
...
...
@@ -73,10 +73,10 @@ NET "sfp_txn_o" LOC= A16;
#NET "TRST_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "CLK0_M2C_P" LOC = E16;
#NET "CLK0_M2C_P" IOSTANDARD = "LVDS_25";
NET "
FMC
_SCL_B" LOC = F7;
NET "
FMC
_SDA_B" LOC = F8;
NET "
FMC
_SCL_B" IOSTANDARD = "LVCMOS25";
NET "
FMC
_SDA_B" IOSTANDARD = "LVCMOS25";
NET "
DIO
_SCL_B" LOC = F7;
NET "
DIO
_SDA_B" LOC = F8;
NET "
DIO
_SCL_B" IOSTANDARD = "LVCMOS25";
NET "
DIO
_SDA_B" IOSTANDARD = "LVCMOS25";
NET "BUTTON1_I" LOC = C22;
NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
...
...
top/spec/wr_nic_top.vhd
View file @
8ccbd8b8
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