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White Rabbit Trigger Distribution
Commit 987f4c60 authored by Tristan Gingold's avatar Tristan Gingold Committed by Dimitris Lampridis
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Add svec_tdc_fd files.

parent 76b8de8b
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builder/hdl/syn/svec_tdc_fd/Manifest.py 0 → 100644
View file @ 987f4c60
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_tdc_fd_top"
syn_project = "svec_tdc_fd.xise"
syn_tool = "ise"
fetchto = "../../../../dependencies"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
files = [
"svec_tdc_fd.ucf",
]
modules = {
"local" : [
"../../top/svec_tdc_fd",
],
}
builder/hdl/syn/svec_tdc_fd/svec_tdc_fd.ucf 0 → 100644
View file @ 987f4c60
#===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_sysreset_n_i" LOC = P4;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
NET "vme_iackout_n_o" LOC = N3;
NET "vme_iackin_n_i" LOC = P7;
NET "vme_iack_n_i" LOC = N1;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[1]" LOC = Y6;
NET "vme_ds_n_i[0]" LOC = Y7;
NET "vme_data_oe_n_o" LOC = P1;
NET "vme_data_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_o[7]" LOC = R7;
NET "vme_irq_o[6]" LOC = AH2;
NET "vme_irq_o[5]" LOC = AF2;
NET "vme_irq_o[4]" LOC = N9;
NET "vme_irq_o[3]" LOC = N10;
NET "vme_irq_o[2]" LOC = AH4;
NET "vme_irq_o[1]" LOC = AG4;
NET "vme_gap_i" LOC = M6;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[13]" LOC = T6;
NET "vme_data_b[12]" LOC = T7;
NET "vme_data_b[11]" LOC = AG5;
NET "vme_data_b[10]" LOC = AE5;
NET "vme_data_b[9]" LOC = Y11;
NET "vme_data_b[8]" LOC = W11;
NET "vme_data_b[7]" LOC = AF6;
NET "vme_data_b[6]" LOC = AE6;
NET "vme_data_b[5]" LOC = Y8;
NET "vme_data_b[4]" LOC = Y9;
NET "vme_data_b[3]" LOC = AE7;
NET "vme_data_b[2]" LOC = AD7;
NET "vme_data_b[1]" LOC = AA9;
NET "vme_data_b[0]" LOC = AA10;
NET "vme_am_i[5]" LOC = V8;
NET "vme_am_i[4]" LOC = AG3;
NET "vme_am_i[3]" LOC = AF3;
NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[21]" LOC = W3;
NET "vme_addr_b[20]" LOC = AA4;
NET "vme_addr_b[19]" LOC = AA5;
NET "vme_addr_b[18]" LOC = Y1;
NET "vme_addr_b[17]" LOC = Y2;
NET "vme_addr_b[16]" LOC = Y3;
NET "vme_addr_b[15]" LOC = Y4;
NET "vme_addr_b[14]" LOC = AC1;
NET "vme_addr_b[13]" LOC = AC3;
NET "vme_addr_b[12]" LOC = AD1;
NET "vme_addr_b[11]" LOC = AD2;
NET "vme_addr_b[10]" LOC = AB3;
NET "vme_addr_b[9]" LOC = AB4;
NET "vme_addr_b[8]" LOC = AD3;
NET "vme_addr_b[7]" LOC = AD4;
NET "vme_addr_b[6]" LOC = AC4;
NET "vme_addr_b[5]" LOC = AC5;
NET "vme_addr_b[4]" LOC = N7;
NET "vme_addr_b[3]" LOC = N8;
NET "vme_addr_b[2]" LOC = AE1;
NET "vme_addr_b[1]" LOC = AE3;
NET "vme_write_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_sysreset_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33";
NET "vme_iackout_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[7]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_gap_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[1]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[0]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[5]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[1]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" LOC = AD28;
NET "rst_n_i" IOSTANDARD = "LVCMOS33";
NET "clk_20m_vcxo_i" LOC = V26;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
NET "clk_125m_pllref_n_i" LOC = AB30;
NET "clk_125m_pllref_p_i" LOC = AB28;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_txp_o" LOC = B23;
NET "sfp_txn_o" LOC = A23;
NET "sfp_rxp_i" LOC = D22;
NET "sfp_rxn_i" LOC = C22;
NET "sfp_los_i" LOC = W25;
NET "sfp_mod_def0_i" LOC = Y26;
NET "sfp_mod_def1_b" LOC = Y27;
NET "sfp_mod_def2_b" LOC = AA24;
NET "sfp_rate_select_o" LOC = W24;
NET "sfp_tx_disable_o" LOC = AA25;
NET "sfp_tx_fault_i" LOC = AA27;
NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock controls
#----------------------------------------
NET "pll20dac_din_o" LOC = U28;
NET "pll20dac_sclk_o" LOC = AA28;
NET "pll20dac_sync_n_o" LOC = N28;
NET "pll25dac_din_o" LOC = P25;
NET "pll25dac_sclk_o" LOC = N27;
NET "pll25dac_sync_n_o" LOC = P26;
NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# SPI FLASH
#----------------------------------------
NET "spi_ncs_o" LOC = AG27;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS33";
NET "spi_sclk_o" LOC = AG26;
NET "spi_sclk_o" IOSTANDARD = "LVCMOS33";
NET "spi_mosi_o" LOC = AH26;
NET "spi_mosi_o" IOSTANDARD = "LVCMOS33";
NET "spi_miso_i" LOC = AH27;
NET "spi_miso_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = U27;
NET "uart_rxd_i" LOC = U25;
NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# 1-wire thermoeter + unique ID
#----------------------------------------
NET "onewire_b" LOC = AC30;
NET "onewire_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Front panel LEDs
#----------------------------------------
NET "fp_led_line_oen_o[0]" LOC = AD26;
NET "fp_led_line_oen_o[1]" LOC = AD27;
NET "fp_led_line_o[0]" LOC = AC27;
NET "fp_led_line_o[1]" LOC = AC28;
NET "fp_led_column_o[0]" LOC = AE30;
NET "fp_led_column_o[1]" LOC = AE27;
NET "fp_led_column_o[2]" LOC = AE28;
NET "fp_led_column_o[3]" LOC = AF28;
NET "fp_led_line_oen_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_oen_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[2]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[3]" IOSTANDARD="LVCMOS33";
#----------------------------------------
# Front panel IOs
#----------------------------------------
NET "fp_gpio1_o" LOC = T28;
NET "fp_gpio2_o" LOC = R30;
NET "fp_gpio3_i" LOC = V27;
NET "fp_gpio4_i" LOC = U29;
NET "fp_gpio1_a2b_o" LOC = T30;
NET "fp_gpio2_a2b_o" LOC = R29;
NET "fp_gpio34_a2b_o" LOC = V28;
NET "fp_term_en_o[1]" LOC = AB1;
NET "fp_term_en_o[2]" LOC = W5;
NET "fp_term_en_o[3]" LOC = W4;
NET "fp_term_en_o[4]" LOC = V4;
NET "fp_gpio1_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio2_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio3_i" IOSTANDARD = "LVCMOS33";
NET "fp_gpio4_i" IOSTANDARD = "LVCMOS33";
NET "fp_gpio1_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio2_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio34_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[1]" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[2]" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[3]" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[4]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Carrier I2C EEPROM
#----------------------------------------
NET "carrier_scl_b" LOC = AC29;
NET "carrier_sda_b" LOC = AA30;
NET "carrier_scl_b" IOSTANDARD = "LVCMOS33";
NET "carrier_sda_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMCs
#----------------------------------------
NET "fmc0_prsntm2c_n_i" LOC = N30;
NET "fmc0_scl_b" LOC = P28;
NET "fmc0_sda_b" LOC = P30;
NET "fmc1_prsntm2c_n_i" LOC = AE29;
NET "fmc1_scl_b" LOC = W29;
NET "fmc1_sda_b" LOC = V30;
NET "fmc1_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
NET "fmc1_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc1_sda_b" IOSTANDARD = "LVCMOS33";
NET "fmc0_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS33";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# All input clocks
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "fp_gpio3_i" TNM_NET = fp_gpio3_i;
TIMESPEC TS_fp_gpio3_i = PERIOD "fp_gpio3_i" 100 ns HIGH 50%;
# relax all paths through syncrhonisers:
# 1. define groups for each clock domain
# 2. define group for all sync chains
# 3. create sync chain groups that exclude one clock domain each
# 4. relax path from each clock domain to respective sync chain group
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_sys_62m5" TNM_NET = clk_sys;
NET "fmc1_clk_125m" TNM_NET = fmc1_clk_125m;
NET "fmc0_clk_125m" TNM_NET = fmc0_clk_125m;
NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_rx_rbclk;
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
TIMEGRP "synchronizers"="sync_ffs" "sync_reg";
TIMEGRP "ref_sync"="synchronizers" EXCEPT "clk_125m_pllref";
TIMEGRP "sys_sync"="synchronizers" EXCEPT "clk_sys";
TIMEGRP "fmc0_sync"="synchronizers" EXCEPT "fmc0_clk_125m";
TIMEGRP "fmc1_sync"="synchronizers" EXCEPT "fmc1_clk_125m";
TIMEGRP "phy_sync"="synchronizers" EXCEPT "phy_rx_rbclk";
TIMESPEC TS_ref_sync_ffs = FROM clk_125m_pllref TO "ref_sync" 20ns DATAPATHONLY;
TIMESPEC TS_sys_sync_ffs = FROM clk_sys TO "sys_sync" 20ns DATAPATHONLY;
TIMESPEC TS_fmc1_sync_ffs = FROM fmc1_clk_125m TO "fmc1_sync" 20ns DATAPATHONLY;
TIMESPEC TS_fmc0_sync_ffs = FROM fmc0_clk_125m TO "fmc0_sync" 20ns DATAPATHONLY;
TIMESPEC TS_phy_sync_ffs = FROM phy_rx_rbclk TO "phy_sync" 20ns DATAPATHONLY;
# Relax the path where TAI time crosses from WR ref to MT sys clock
# This is already synced via a gc_pulse_synchronizer, which makes sure that
# TAI WR ref value is stable when sampled by the MT sys clock
NET "cmp_mock_turtle/gen_cpus[*].U_CPU_Block/tm_p_sys" TNM_NET = "tm_mt_sync";
TIMESPEC TS_tm_mt_sync = FROM clk_125m_pllref TO "tm_mt_sync" 20ns DATAPATHONLY;
# Relax timing from spll_aligner outputs cref and cin (driven by ref clock)
# to the spll registers (driven by sys clock). The two sides are already sychronized
# via a gc_pulse_synchronizer, which makes sure that cref and cin are stable
# when sampled by the sys clock.
NET "*/WRPC/U_SOFTPLL/U_Wrapped_Softpll/aligner_sample_cref(*)" TNM_NET = "wr_spll_sync";
NET "*/WRPC/U_SOFTPLL/U_Wrapped_Softpll/aligner_sample_cin(*)" TNM_NET = "wr_spll_sync";
TIMESPEC TS_wr_spll_sync = FROM clk_125m_pllref TO "wr_spll_sync" 20ns DATAPATHONLY;
# External async resets
NET "rst_n_i" TIG;
NET "vme_sysreset_n_i" TIG;
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "fmc0_tdc_acam_refclk_p_i" LOC = "H15";
NET "fmc0_tdc_acam_refclk_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_acam_refclk_n_i" LOC = "G15";
NET "fmc0_tdc_acam_refclk_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_125m_clk_p_i" LOC = "E16";
NET "fmc0_tdc_125m_clk_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_125m_clk_n_i" LOC = "D16";
NET "fmc0_tdc_125m_clk_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_led_trig1_o" LOC = "H13";
NET "fmc0_tdc_led_trig1_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig2_o" LOC = "H11";
NET "fmc0_tdc_led_trig2_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig3_o" LOC = "G11";
NET "fmc0_tdc_led_trig3_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_1_o" LOC = "C16";
NET "fmc0_tdc_term_en_1_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_2_o" LOC = "A16";
NET "fmc0_tdc_term_en_2_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_ef1_i" LOC = "F19";
NET "fmc0_tdc_ef1_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_ef2_i" LOC = "E19";
NET "fmc0_tdc_ef2_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_3_o" LOC = "F15";
NET "fmc0_tdc_term_en_3_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_4_o" LOC = "E15";
NET "fmc0_tdc_term_en_4_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_5_o" LOC = "F13";
NET "fmc0_tdc_term_en_5_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_status_o" LOC = "E13";
NET "fmc0_tdc_led_status_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig4_o" LOC = "L11";
NET "fmc0_tdc_led_trig4_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig5_o" LOC = "K11";
NET "fmc0_tdc_led_trig5_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_sclk_o" LOC = "M15";
NET "fmc0_tdc_pll_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_dac_sync_n_o" LOC = "K15";
NET "fmc0_tdc_pll_dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_cs_n_o" LOC = "L14";
NET "fmc0_tdc_pll_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_cs_n_o" LOC = "K14";
NET "fmc0_tdc_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_err_flag_i" LOC = "H16";
NET "fmc0_tdc_err_flag_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_int_flag_i" LOC = "G16";
NET "fmc0_tdc_int_flag_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_start_dis_o" LOC = "F11";
NET "fmc0_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_stop_dis_o" LOC = "E11";
NET "fmc0_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_sdo_i" LOC = "L13";
NET "fmc0_tdc_pll_sdo_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_status_i" LOC = "E9";
NET "fmc0_tdc_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_sdi_o" LOC = "M13";
NET "fmc0_tdc_pll_sdi_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_start_from_fpga_o" LOC = "F9";
NET "fmc0_tdc_start_from_fpga_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_start_from_fpga_o" SLEW = SLOW;
NET "fmc0_tdc_start_from_fpga_o" DRIVE = 4;
NET "fmc0_tdc_data_bus_io[27]" LOC = "E17";
NET "fmc0_tdc_data_bus_io[27]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[26]" LOC = "F17";
NET "fmc0_tdc_data_bus_io[26]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[25]" LOC = "F18";
NET "fmc0_tdc_data_bus_io[25]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[24]" LOC = "G18";
NET "fmc0_tdc_data_bus_io[24]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[23]" LOC = "F20";
NET "fmc0_tdc_data_bus_io[23]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[22]" LOC = "G20";
NET "fmc0_tdc_data_bus_io[22]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[21]" LOC = "E21";
NET "fmc0_tdc_data_bus_io[21]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[20]" LOC = "F21";
NET "fmc0_tdc_data_bus_io[20]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[19]" LOC = "K21";
NET "fmc0_tdc_data_bus_io[19]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[18]" LOC = "L21";
NET "fmc0_tdc_data_bus_io[18]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[17]" LOC = "L20";
NET "fmc0_tdc_data_bus_io[17]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[16]" LOC = "M20";
NET "fmc0_tdc_data_bus_io[16]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[15]" LOC = "F22";
NET "fmc0_tdc_data_bus_io[15]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[14]" LOC = "G22";
NET "fmc0_tdc_data_bus_io[14]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[13]" LOC = "L19";
NET "fmc0_tdc_data_bus_io[13]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[12]" LOC = "M19";
NET "fmc0_tdc_data_bus_io[12]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[11]" LOC = "E23";
NET "fmc0_tdc_data_bus_io[11]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[10]" LOC = "F23";
NET "fmc0_tdc_data_bus_io[10]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[9]" LOC = "A25";
NET "fmc0_tdc_data_bus_io[9]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[8]" LOC = "B25";
NET "fmc0_tdc_data_bus_io[8]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[7]" LOC = "G21";
NET "fmc0_tdc_data_bus_io[7]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[6]" LOC = "C24";
NET "fmc0_tdc_data_bus_io[6]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[5]" LOC = "H21";
NET "fmc0_tdc_data_bus_io[5]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[4]" LOC = "D24";
NET "fmc0_tdc_data_bus_io[4]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[3]" LOC = "D25";
NET "fmc0_tdc_data_bus_io[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[2]" LOC = "E25";
NET "fmc0_tdc_data_bus_io[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[1]" LOC = "H22";
NET "fmc0_tdc_data_bus_io[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[0]" LOC = "J22";
NET "fmc0_tdc_data_bus_io[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[3]" LOC = "F14";
NET "fmc0_tdc_address_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[2]" LOC = "G14";
NET "fmc0_tdc_address_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[1]" LOC = "H14";
NET "fmc0_tdc_address_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[0]" LOC = "J14";
NET "fmc0_tdc_address_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_oe_n_o" LOC = "G12";
NET "fmc0_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_oe_n_o" SLEW = SLOW;
NET "fmc0_tdc_oe_n_o" DRIVE = 4;
NET "fmc0_tdc_rd_n_o" LOC = "A15";
NET "fmc0_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_rd_n_o" SLEW = SLOW;
NET "fmc0_tdc_rd_n_o" DRIVE = 4;
NET "fmc0_tdc_wr_n_o" LOC = "B15";
NET "fmc0_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_wr_n_o" SLEW = SLOW;
NET "fmc0_tdc_wr_n_o" DRIVE = 4;
NET "fmc0_tdc_enable_inputs_o" LOC = "J12";
NET "fmc0_tdc_enable_inputs_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_onewire_b" LOC = "H12";
NET "fmc0_tdc_onewire_b" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# input clocks
NET "fmc0_tdc_125m_clk_n_i" TNM_NET = fmc0_tdc_125m_clk_n_i;
TIMESPEC TS_fmc0_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_125m_clk_n_i" 8 ns HIGH 50%;
# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 1
NET "fmc1_fd_clk_ref_p_i" LOC = "AH16";
NET "fmc1_fd_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_clk_ref_n_i" LOC = "AK16";
NET "fmc1_fd_clk_ref_n_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_tdc_start_p_i" LOC = "AF16";
NET "fmc1_fd_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_tdc_start_n_i" LOC = "AG16";
NET "fmc1_fd_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_delay_len_o[3]" LOC = "AB21";
NET "fmc1_fd_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[3]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[3]" DRIVE = 4;
NET "fmc1_fd_delay_len_o[2]" LOC = "AC21";
NET "fmc1_fd_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[2]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[2]" DRIVE = 4;
NET "fmc1_fd_delay_len_o[1]" LOC = "AD24";
NET "fmc1_fd_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[1]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[1]" DRIVE = 4;
NET "fmc1_fd_delay_len_o[0]" LOC = "AC24";
NET "fmc1_fd_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[0]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[0]" DRIVE = 4;
NET "fmc1_fd_delay_pulse_o[3]" LOC = "AE22";
NET "fmc1_fd_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_pulse_o[1]" LOC = "AD17";
NET "fmc1_fd_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_pulse_o[2]" LOC = "AD22";
NET "fmc1_fd_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_pulse_o[0]" LOC = "AB17";
NET "fmc1_fd_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[3]" LOC = "AA19";
NET "fmc1_fd_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[3]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[3]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[1]" LOC = "W19";
NET "fmc1_fd_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[1]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[1]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[7]" LOC = "Y21";
NET "fmc1_fd_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[7]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[7]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[5]" LOC = "W20";
NET "fmc1_fd_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[5]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[5]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[9]" LOC = "AA22";
NET "fmc1_fd_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[9]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[9]" DRIVE = 4;
NET "fmc1_fd_spi_mosi_o" LOC = "AB20";
NET "fmc1_fd_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_sclk_o" LOC = "AC19";
NET "fmc1_fd_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_oe_n_o" LOC = "AF25";
NET "fmc1_fd_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_start_dis_o" LOC = "AE24";
NET "fmc1_fd_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_gpio_n_o" LOC = "AE19";
NET "fmc1_fd_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_cal_pulse_o" LOC = "AE23";
NET "fmc1_fd_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_clk_o" LOC = "AE21";
NET "fmc1_fd_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_wr_n_o" LOC = "AC16";
NET "fmc1_fd_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_alutrigger_o" LOC = "AB14";
NET "fmc1_fd_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_led_trig_o" LOC = "Y17";
NET "fmc1_fd_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[26]" LOC = "Y15";
NET "fmc1_fd_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[24]" LOC = "AC15";
NET "fmc1_fd_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[20]" LOC = "AE15";
NET "fmc1_fd_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[22]" LOC = "Y16";
NET "fmc1_fd_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[18]" LOC = "Y14";
NET "fmc1_fd_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[16]" LOC = "W14";
NET "fmc1_fd_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[10]" LOC = "AB12";
NET "fmc1_fd_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[14]" LOC = "AD12";
NET "fmc1_fd_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[8]" LOC = "AD10";
NET "fmc1_fd_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[12]" LOC = "AE11";
NET "fmc1_fd_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[3]" LOC = "AJ15";
NET "fmc1_fd_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[5]" LOC = "AE13";
NET "fmc1_fd_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[7]" LOC = "AC11";
NET "fmc1_fd_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[2]" LOC = "AG8";
NET "fmc1_fd_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_trig_a_i" LOC = "AJ17";
NET "fmc1_fd_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[2]" LOC = "AB19";
NET "fmc1_fd_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[2]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[2]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[0]" LOC = "Y19";
NET "fmc1_fd_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[0]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[0]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[6]" LOC = "AA21";
NET "fmc1_fd_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[6]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[6]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[4]" LOC = "Y20";
NET "fmc1_fd_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[4]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[4]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[8]" LOC = "AC22";
NET "fmc1_fd_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[8]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[8]" DRIVE = 4;
NET "fmc1_fd_spi_miso_i" LOC = "AC20";
NET "fmc1_fd_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_pll_n_o" LOC = "AD19";
NET "fmc1_fd_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_dac_n_o" LOC = "AG25";
NET "fmc1_fd_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_stop_dis_o" LOC = "AF24";
NET "fmc1_fd_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_ext_rst_n_o" LOC = "AF19";
NET "fmc1_fd_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_pll_status_i" LOC = "AF23";
NET "fmc1_fd_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_fb_out_i" LOC = "AF21";
NET "fmc1_fd_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_rd_n_o" LOC = "AD16";
NET "fmc1_fd_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_emptyf_i" LOC = "AC14";
NET "fmc1_fd_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_onewire_b" LOC = "AA17";
NET "fmc1_fd_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[27]" LOC = "AA15";
NET "fmc1_fd_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[25]" LOC = "AD15";
NET "fmc1_fd_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[21]" LOC = "AF15";
NET "fmc1_fd_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[23]" LOC = "AB16";
NET "fmc1_fd_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[19]" LOC = "AA14";
NET "fmc1_fd_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[17]" LOC = "Y13";
NET "fmc1_fd_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[11]" LOC = "AC12";
NET "fmc1_fd_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[15]" LOC = "AE12";
NET "fmc1_fd_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[9]" LOC = "AE10";
NET "fmc1_fd_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[13]" LOC = "AF11";
NET "fmc1_fd_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[1]" LOC = "AK15";
NET "fmc1_fd_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[4]" LOC = "AF13";
NET "fmc1_fd_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[6]" LOC = "AD11";
NET "fmc1_fd_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[0]" LOC = "AH8";
NET "fmc1_fd_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_fb_in_i" LOC = "AK17";
NET "fmc1_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# All input clocks
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
builder/hdl/top/svec_tdc_fd/Manifest.py 0 → 100644
View file @ 987f4c60
files = [
"svec_tdc_fd_top.vhd",
]
fetchto = "../../../../dependencies"
modules = {
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/mock-turtle.git",
"git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git",
"git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git",
],
}
builder/hdl/top/svec_tdc_fd/svec_tdc_fd_top.vhd 0 → 100644
View file @ 987f4c60
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- LHC Instability Trigger Distribution (LIST)
-- https://ohwr.org/projects/list
--------------------------------------------------------------------------------
--
-- unit name: svec_list_top
--
-- description: Top entity for LHC Instability Trigger Distribution project
--
-- Top level design of the SVEC-based LIST WR trigger distribution node, with
-- an FMC TDC in slot and an FMC Fine Delay in slot 2.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2014-2018
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.vme64x_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
use work.wr_fabric_pkg.all;
use work.mt_mqueue_pkg.all;
use work.mock_turtle_pkg.all;
use work.synthesis_descriptor.all;
use work.tdc_core_pkg.all;
use work.fine_delay_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity svec_tdc_fd_top is
generic (
g_WR_DPRAM_INITF : string := "../../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram";
g_MT_CPU0_INITF : string := "../../../../software/firmware/tdc/wrtd-rt-tdc.bram";
g_MT_CPU1_INITF : string := "../../../../software/firmware/fd/wrtd-rt-fd.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the
-- testbench. Its purpose is to reduce some internal counters/timeouts
-- to speed up simulations.
g_SIMULATION : integer := 0;
-- Bypass VME core, useful only in simulation
g_SIM_BYPASS_VME : boolean := FALSE);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset from system fpga
rst_n_i : in std_logic;
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
---------------------------------------------------------------------------
-- VME interface
---------------------------------------------------------------------------
-- Bypass VME core, useful only in simulation
-- synthesis translate_off
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
sim_wb_o : out t_wishbone_slave_out;
-- synthesis translate_on
vme_write_n_i : in std_logic;
vme_sysreset_n_i : in std_logic;
vme_retry_oe_o : out std_logic;
vme_retry_n_o : out std_logic;
vme_lword_n_b : inout std_logic;
vme_iackout_n_o : out std_logic;
vme_iackin_n_i : in std_logic;
vme_iack_n_i : in std_logic;
vme_gap_i : in std_logic;
vme_dtack_oe_o : out std_logic;
vme_dtack_n_o : out std_logic;
vme_ds_n_i : in std_logic_vector(1 downto 0);
vme_data_oe_n_o : out std_logic;
vme_data_dir_o : out std_logic;
vme_berr_o : out std_logic;
vme_as_n_i : in std_logic;
vme_addr_oe_n_o : out std_logic;
vme_addr_dir_o : out std_logic;
vme_irq_o : out std_logic_vector(7 downto 1);
vme_ga_i : in std_logic_vector(4 downto 0);
vme_data_b : inout std_logic_vector(31 downto 0);
vme_am_i : in std_logic_vector(5 downto 0);
vme_addr_b : inout std_logic_vector(31 downto 1);
---------------------------------------------------------------------------
-- SPI interfaces to DACs
---------------------------------------------------------------------------
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic;
pll25dac_din_o : out std_logic;
pll25dac_sclk_o : out std_logic;
pll25dac_sync_n_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
---------------------------------------------------------------------------
-- Carrier I2C EEPROM
---------------------------------------------------------------------------
carrier_scl_b : inout std_logic;
carrier_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- SPI (flash is connected to SFPGA and routed to AFPGA
-- once the boot process is complete)
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- Carrier front panel LEDs and IOs
---------------------------------------------------------------------------
fp_led_line_oen_o : out std_logic_vector(1 downto 0);
fp_led_line_o : out std_logic_vector(1 downto 0);
fp_led_column_o : out std_logic_vector(3 downto 0);
fp_gpio1_o : out std_logic; -- PPS output
fp_gpio2_o : out std_logic; -- Ref clock div2 output
fp_gpio3_i : in std_logic; -- ext 10MHz clock input
fp_gpio4_i : in std_logic; -- ext PPS input
fp_term_en_o : out std_logic_vector(4 downto 1);
fp_gpio1_a2b_o : out std_logic;
fp_gpio2_a2b_o : out std_logic;
fp_gpio34_a2b_o : out std_logic;
---------------------------------------------------------------------------
-- FMC slot 0 pins (TDC mezzanine)
---------------------------------------------------------------------------
-- TDC1 PLL AD9516 and DAC AD5662 interface
fmc0_tdc_pll_sclk_o : out std_logic;
fmc0_tdc_pll_sdi_o : out std_logic;
fmc0_tdc_pll_cs_n_o : out std_logic;
fmc0_tdc_pll_dac_sync_n_o : out std_logic;
fmc0_tdc_pll_sdo_i : in std_logic;
fmc0_tdc_pll_status_i : in std_logic;
fmc0_tdc_125m_clk_p_i : in std_logic;
fmc0_tdc_125m_clk_n_i : in std_logic;
fmc0_tdc_acam_refclk_p_i : in std_logic;
fmc0_tdc_acam_refclk_n_i : in std_logic;
-- TDC1 ACAM timing interface
fmc0_tdc_start_from_fpga_o : out std_logic;
fmc0_tdc_err_flag_i : in std_logic;
fmc0_tdc_int_flag_i : in std_logic;
fmc0_tdc_start_dis_o : out std_logic;
fmc0_tdc_stop_dis_o : out std_logic;
-- TDC1 ACAM data interface
fmc0_tdc_data_bus_io : inout std_logic_vector(27 downto 0);
fmc0_tdc_address_o : out std_logic_vector(3 downto 0);
fmc0_tdc_cs_n_o : out std_logic;
fmc0_tdc_oe_n_o : out std_logic;
fmc0_tdc_rd_n_o : out std_logic;
fmc0_tdc_wr_n_o : out std_logic;
fmc0_tdc_ef1_i : in std_logic;
fmc0_tdc_ef2_i : in std_logic;
-- TDC1 Input Logic
fmc0_tdc_enable_inputs_o : out std_logic;
fmc0_tdc_term_en_1_o : out std_logic;
fmc0_tdc_term_en_2_o : out std_logic;
fmc0_tdc_term_en_3_o : out std_logic;
fmc0_tdc_term_en_4_o : out std_logic;
fmc0_tdc_term_en_5_o : out std_logic;
-- TDC1 1-wire UniqueID & Thermometer
fmc0_tdc_onewire_b : inout std_logic;
-- TDC1 EEPROM I2C
fmc0_tdc_scl_b : inout std_logic;
fmc0_tdc_sda_b : inout std_logic;
-- TDC1 LEDs
fmc0_tdc_led_status_o : out std_logic;
fmc0_tdc_led_trig1_o : out std_logic;
fmc0_tdc_led_trig2_o : out std_logic;
fmc0_tdc_led_trig3_o : out std_logic;
fmc0_tdc_led_trig4_o : out std_logic;
fmc0_tdc_led_trig5_o : out std_logic;
-- TDC1 Input channels
-- also arriving to the FPGA (not used for the moment)
fmc0_tdc_in_fpga_1_i : in std_logic;
fmc0_tdc_in_fpga_2_i : in std_logic;
fmc0_tdc_in_fpga_3_i : in std_logic;
fmc0_tdc_in_fpga_4_i : in std_logic;
fmc0_tdc_in_fpga_5_i : in std_logic;
---------------------------------------------------------------------------
-- FMC slot 1 pins (FDELAY mezzanine)
---------------------------------------------------------------------------
fmc1_fd_tdc_start_p_i : in std_logic;
fmc1_fd_tdc_start_n_i : in std_logic;
fmc1_fd_clk_ref_p_i : in std_logic;
fmc1_fd_clk_ref_n_i : in std_logic;
fmc1_fd_trig_a_i : in std_logic;
fmc1_fd_tdc_cal_pulse_o : out std_logic;
fmc1_fd_tdc_d_b : inout std_logic_vector(27 downto 0);
fmc1_fd_tdc_emptyf_i : in std_logic;
fmc1_fd_tdc_alutrigger_o : out std_logic;
fmc1_fd_tdc_wr_n_o : out std_logic;
fmc1_fd_tdc_rd_n_o : out std_logic;
fmc1_fd_tdc_oe_n_o : out std_logic;
fmc1_fd_led_trig_o : out std_logic;
fmc1_fd_tdc_start_dis_o : out std_logic;
fmc1_fd_tdc_stop_dis_o : out std_logic;
fmc1_fd_spi_cs_dac_n_o : out std_logic;
fmc1_fd_spi_cs_pll_n_o : out std_logic;
fmc1_fd_spi_cs_gpio_n_o : out std_logic;
fmc1_fd_spi_sclk_o : out std_logic;
fmc1_fd_spi_mosi_o : out std_logic;
fmc1_fd_spi_miso_i : in std_logic;
fmc1_fd_delay_len_o : out std_logic_vector(3 downto 0);
fmc1_fd_delay_val_o : out std_logic_vector(9 downto 0);
fmc1_fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fmc1_fd_dmtd_clk_o : out std_logic;
fmc1_fd_dmtd_fb_in_i : in std_logic;
fmc1_fd_dmtd_fb_out_i : in std_logic;
fmc1_fd_pll_status_i : in std_logic;
fmc1_fd_ext_rst_n_o : out std_logic;
fmc1_fd_onewire_b : inout std_logic;
fmc0_prsntm2c_n_i : in std_logic;
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
fmc1_prsntm2c_n_i : in std_logic;
fmc1_scl_b : inout std_logic;
fmc1_sda_b : inout std_logic);
end entity svec_tdc_fd_top;
architecture arch of svec_tdc_fd_top is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Number of masters attached to the primary wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves attached to the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 2 + 3;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_VME : integer := 0;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_VIC : integer := 0;
constant c_WB_SLAVE_FMC0 : integer := 1;
constant c_WB_SLAVE_FMC1 : integer := 2;
constant c_WB_SLAVE_MT : integer := 2 + 1;
constant c_WB_SLAVE_WRC : integer := 2 + 2;
constant c_WB_DESC_SYN : integer := 2 + 3;
constant c_WB_DESC_URL : integer := 2 + 4;
-- sdb header address on primary crossbar
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_wrc_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_tdc0_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"00007FFF", x"00000000");
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := (
c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00002000"),
c_WB_SLAVE_FMC0 => f_sdb_embed_bridge(c_tdc0_bridge_sdb, x"00010000"),
c_WB_SLAVE_FMC1 => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00018000"),
c_WB_SLAVE_MT => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000"),
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00040000"),
c_WB_DESC_SYN => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO),
c_WB_DESC_URL => f_sdb_embed_repo_url(c_SDB_REPO_URL));
-- not really used, will be reprogrammed by software
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 5) := (
0 => x"00013000", -- FMC0
1 => x"00018000", -- FMC1
2 => x"00020000", -- MT Mqueue in interrupt
3 => x"00020001", -- MT Mqueue out interrupt
4 => x"00020002", -- MT Console interrupt
5 => x"00020003"); -- MT Notify interrupt
constant c_FMC_MUX_ADDR : t_wishbone_address_array(0 downto 0) :=
(0 => x"00000000");
constant c_FMC_MUX_MASK : t_wishbone_address_array(0 downto 0) :=
(0 => x"10000000");
constant c_mt_config : t_mt_config :=
(
app_id => x"115790de",
cpu_count => 2,
cpu_config => (
0 => (
memsize => 8192,
hmq_config => (
slot_count => 1,
slot_config => (
0 => (
entries_bits => 4,
width_bits => 7,
header_bits => 2,
endpoint_id => x"0000_0000",
enable_config_space => FALSE),
others => c_DUMMY_MT_MQUEUE_SLOT)),
rmq_config => (
slot_count => 1,
slot_config => (
0 => (
entries_bits => 4,
width_bits => 7,
header_bits => 4,
endpoint_id => x"0000_0000",
enable_config_space => TRUE),
others => c_DUMMY_MT_MQUEUE_SLOT))),
1 => (
memsize => 8192,
hmq_config => (
slot_count => 1,
slot_config => (
0 => (
entries_bits => 4,
width_bits => 7,
header_bits => 2,
endpoint_id => x"0000_0000",
enable_config_space => FALSE),
others => c_DUMMY_MT_MQUEUE_SLOT)),
rmq_config => (
slot_count => 1,
slot_config => (
0 => (
entries_bits => 4,
width_bits => 7,
header_bits => 4,
endpoint_id => x"0000_0000",
enable_config_space => TRUE),
others => c_DUMMY_MT_MQUEUE_SLOT))),
others => (
0, c_MT_DEFAULT_MQUEUE_CONFIG, c_MT_DEFAULT_MQUEUE_CONFIG)),
shared_mem_size => 256
);
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Wishbone buse(s) from masters attached to crossbar
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- Wishbone buse(s) to slaves attached to crossbar
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
-- clock and reset
signal areset_n : std_logic;
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ref_div2 : std_logic;
signal clk_ext_ref : std_logic;
signal fmc0_clk_125m : std_logic;
signal fmc1_clk_125m : std_logic;
attribute keep : string;
attribute keep of clk_sys_62m5 : signal is "TRUE";
attribute keep of clk_ref_125m : signal is "TRUE";
attribute keep of fmc0_clk_125m : signal is "TRUE";
attribute keep of fmc1_clk_125m : signal is "TRUE";
-- I2C EEPROM
signal eeprom_sda_in : std_logic;
signal eeprom_sda_out : std_logic;
signal eeprom_scl_in : std_logic;
signal eeprom_scl_out : std_logic;
-- VME
signal vme_data_b_out : std_logic_vector(31 downto 0);
signal vme_addr_b_out : std_logic_vector(31 downto 1);
signal vme_lword_n_b_out : std_logic;
signal Vme_data_dir_int : std_logic;
signal vme_addr_dir_int : std_logic;
signal vme_ga : std_logic_vector(5 downto 0);
signal vme_berr_n : std_logic;
signal vme_irq_n : std_logic_vector(7 downto 1);
signal vme_access_led : std_logic;
-- SFP
signal sfp_sda_in : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
-- LEDs and GPIO
signal pps : std_logic;
signal pps_led : std_logic;
signal pps_ext_in : std_logic;
signal svec_led : std_logic_vector(15 downto 0);
signal wr_led_link : std_logic;
signal wr_led_act : std_logic;
-- VIC
signal fmc_host_irq : std_logic_vector(1 downto 0) := "00";
signal mt_hmq_in_irq : std_logic;
signal mt_hmq_out_irq : std_logic;
signal mt_console_irq : std_logic;
signal mt_notify_irq : std_logic;
signal vic_master_irq : std_logic;
-- MT endpoints
signal rmq_endpoint_out : t_mt_rmq_endpoint_iface_out;
signal rmq_endpoint_in : t_mt_rmq_endpoint_iface_in;
signal rmq_src_in : t_mt_stream_source_in;
signal rmq_src_out : t_mt_stream_source_out;
signal rmq_src_cfg_in : t_mt_stream_config_in;
signal rmq_src_cfg_out : t_mt_stream_config_out;
signal rmq_snk_in : t_mt_stream_sink_in;
signal rmq_snk_out : t_mt_stream_sink_out;
signal rmq_snk_cfg_in : t_mt_stream_config_in;
signal rmq_snk_cfg_out : t_mt_stream_config_out;
-- MT fabric.
signal eth_tx_out : t_wrf_source_out;
signal eth_tx_in : t_wrf_source_in;
signal eth_rx_out : t_wrf_sink_out;
signal eth_rx_in : t_wrf_sink_in;
-- MT Dedicated WB interfaces to FMCs
signal fmc_dp_wb_out : t_wishbone_master_out_array(0 to 2 - 1);
signal fmc_dp_wb_in : t_wishbone_master_in_array(0 to 2 - 1);
-- WRPC TM interface and aux clocks
signal tm_link_up : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
signal tm_clk_aux_lock_en : std_logic_vector(1 downto 0);
signal tm_clk_aux_locked : std_logic_vector(1 downto 0);
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_dac_wr : std_logic_vector(1 downto 0);
-- MT TM interface
signal tm : t_mt_timing_if;
signal fmc0_scl_out : std_logic := '1';
signal fmc0_sda_out : std_logic := '1';
signal fmc1_scl_out : std_logic := '1';
signal fmc1_sda_out : std_logic := '1';
attribute iob : string;
attribute iob of pps : signal is "FORCE";
-- Muxed Host and MT WB interface to FMC1
signal fmc1_mux_wb_out : t_wishbone_master_out;
signal fmc1_mux_wb_in : t_wishbone_master_in;
-- Misc FMC signals
signal fmc1_fd_tdc_start : std_logic;
signal ddr1_pll_reset : std_logic;
signal ddr1_pll_locked : std_logic;
signal fmc1_fd_pll_status : std_logic;
signal fmc1_fd_tdc_data_out : std_logic_vector(27 downto 0);
signal fmc1_fd_tdc_data_in : std_logic_vector(27 downto 0);
signal fmc1_fd_tdc_data_oe : std_logic;
signal fmc1_fd_owr_en, fmc1_fd_owr_in : std_logic;
signal fmc1_fd_scl_in : std_logic;
signal fmc1_fd_sda_in : std_logic;
signal fmc1_clk_125m_180 : std_logic;
begin -- architecture arch
-----------------------------------------------------------------------------
-- System reset
-----------------------------------------------------------------------------
areset_n <= vme_sysreset_n_i and rst_n_i;
-----------------------------------------------------------------------------
-- Primary wishbone Crossbar
-----------------------------------------------------------------------------
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map (
g_num_masters => c_NUM_WB_MASTERS,
g_num_slaves => c_NUM_WB_SLAVES,
g_registered => TRUE,
g_wraparound => TRUE,
g_layout => c_WB_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
-----------------------------------------------------------------------------
-- VME64x Core (WB Master)
-----------------------------------------------------------------------------
gen_with_vme64_core : if not g_SIM_BYPASS_VME generate
cmp_vme_core : xvme64x_core
generic map (
g_CLOCK_PERIOD => 16,
g_DECODE_AM => TRUE,
g_USER_CSR_EXT => FALSE,
g_WB_GRANULARITY => BYTE,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
vme_i.as_n => vme_as_n_i,
vme_i.rst_n => vme_sysreset_n_i,
vme_i.write_n => vme_write_n_i,
vme_i.am => vme_am_i,
vme_i.ds_n => vme_ds_n_i,
vme_i.ga => vme_ga,
vme_i.lword_n => vme_lword_n_b,
vme_i.addr => vme_addr_b,
vme_i.data => vme_data_b,
vme_i.iack_n => vme_iack_n_i,
vme_i.iackin_n => vme_iackin_n_i,
vme_o.berr_n => vme_berr_n,
vme_o.dtack_n => vme_dtack_n_o,
vme_o.retry_n => vme_retry_n_o,
vme_o.retry_oe => vme_retry_oe_o,
vme_o.lword_n => vme_lword_n_b_out,
vme_o.data => vme_data_b_out,
vme_o.addr => vme_addr_b_out,
vme_o.irq_n => vme_irq_n,
vme_o.iackout_n => vme_iackout_n_o,
vme_o.dtack_oe => vme_dtack_oe_o,
vme_o.data_dir => vme_data_dir_int,
vme_o.data_oe_n => vme_data_oe_n_o,
vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_o => cnx_master_out(c_WB_MASTER_VME),
wb_i => cnx_master_in(c_WB_MASTER_VME),
int_i => vic_master_irq);
vme_ga <= vme_gap_i & vme_ga_i;
vme_berr_o <= not vme_berr_n;
vme_irq_o <= not vme_irq_n;
-- VME tri-state buffers
vme_data_b <= vme_data_b_out when vme_data_dir_int = '1' else (others => 'Z');
vme_addr_b <= vme_addr_b_out when vme_addr_dir_int = '1' else (others => 'Z');
vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';
vme_addr_dir_o <= vme_addr_dir_int;
vme_data_dir_o <= vme_data_dir_int;
end generate gen_with_vme64_core;
gen_without_vme64_core : if g_SIM_BYPASS_VME generate
-- synthesis translate_off
cnx_master_out(c_WB_MASTER_VME) <= sim_wb_i;
sim_wb_o <= cnx_master_in(c_WB_MASTER_VME);
-- synthesis translate_on
end generate gen_without_vme64_core;
cmp_vme_led_extend : gc_extend_pulse
generic map (
g_width => 5000000)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => cnx_slave_in(c_WB_MASTER_VME).cyc,
extended_o => vme_access_led);
-----------------------------------------------------------------------------
-- Vectored Interrupt Controller (WB Slave)
-----------------------------------------------------------------------------
cmp_vic : xwb_vic
generic map (
g_INTERFACE_MODE => PIPELINED,
g_ADDRESS_GRANULARITY => BYTE,
g_NUM_INTERRUPTS => 6,
g_INIT_VECTORS => c_VIC_VECTOR_TABLE)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in(c_WB_SLAVE_VIC),
slave_o => cnx_slave_out(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_host_irq(0),
irqs_i(1) => fmc_host_irq(1),
irqs_i(2) => mt_hmq_in_irq,
irqs_i(3) => mt_hmq_out_irq,
irqs_i(4) => mt_console_irq,
irqs_i(5) => mt_notify_irq,
irq_master_o => vic_master_irq);
-----------------------------------------------------------------------------
-- Mock Turtle (WB Slave)
-----------------------------------------------------------------------------
cmp_mock_turtle : entity work.mock_turtle_core
generic map (
g_CONFIG => c_MT_CONFIG,
g_CPU0_IRAM_INITF => g_MT_CPU0_INITF,
g_CPU1_IRAM_INITF => g_MT_CPU1_INITF,
g_WITH_WHITE_RABBIT => TRUE)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
sp_master_o => open,
sp_master_i => c_DUMMY_WB_MASTER_IN,
dp_master_o => fmc_dp_wb_out,
dp_master_i => fmc_dp_wb_in,
rmq_endpoint_o => rmq_endpoint_out,
rmq_endpoint_i => rmq_endpoint_in,
host_slave_i => cnx_slave_in(c_WB_SLAVE_MT),
host_slave_o => cnx_slave_out(c_WB_SLAVE_MT),
clk_ref_i => clk_ref_125m,
tm_i => tm,
hmq_in_irq_o => mt_hmq_in_irq,
hmq_out_irq_o => mt_hmq_out_irq,
notify_irq_o => mt_notify_irq,
console_irq_o => mt_console_irq);
tm.cycles <= tm_cycles;
tm.tai <= tm_tai;
tm.time_valid <= tm_time_valid;
tm.link_up <= tm_link_up;
tm.aux_locked(1 downto 0) <= tm_clk_aux_locked;
tm.aux_locked(7 downto 2) <= (others => '0');
cmp_eth_endpoint : entity work.mt_ep_ethernet_single
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
rmq_src_i => rmq_src_in,
rmq_src_o => rmq_src_out,
rmq_src_config_i => rmq_snk_cfg_out,
rmq_src_config_o => rmq_snk_cfg_in,
rmq_snk_i => rmq_snk_in,
rmq_snk_o => rmq_snk_out,
rmq_snk_config_i => rmq_src_cfg_out,
rmq_snk_config_o => rmq_src_cfg_in,
eth_src_o => eth_tx_out,
eth_src_i => eth_tx_in,
eth_snk_o => eth_rx_out,
eth_snk_i => eth_rx_in);
p_rmq_assign : process (rmq_endpoint_out, rmq_snk_cfg_in, rmq_snk_out,
rmq_src_cfg_in, rmq_src_out) is
begin
rmq_endpoint_in <= c_MT_RMQ_ENDPOINT_IFACE_IN_DEFAULT_VALUE;
-- WR->MT (RX, to MT CPU1)
rmq_src_in <= rmq_endpoint_out.snk_out(1)(0);
rmq_endpoint_in.snk_in(1)(0) <= rmq_src_out;
rmq_snk_cfg_out <= rmq_endpoint_out.snk_config_out(1)(0);
rmq_endpoint_in.snk_config_in(1)(0) <= rmq_snk_cfg_in;
-- MT->WR (TX, from MT CPU0)
rmq_snk_in <= rmq_endpoint_out.src_out(0)(0);
rmq_endpoint_in.src_in(0)(0) <= rmq_snk_out;
rmq_src_cfg_out <= rmq_endpoint_out.src_config_out(0)(0);
rmq_endpoint_in.src_config_in(0)(0) <= rmq_src_cfg_in;
end process p_rmq_assign;
-----------------------------------------------------------------------------
-- The WR PTP core SVEC board package (WB Slave)
-----------------------------------------------------------------------------
cmp_xwrc_board_svec : xwrc_board_svec
generic map (
g_simulation => g_simulation,
g_dpram_initf => g_WR_DPRAM_INITF,
g_aux_clks => 2)
port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_i => clk_ext_ref,
clk_aux_i(0) => fmc0_clk_125m,
clk_aux_i(1) => fmc1_clk_125m,
areset_n_i => areset_n,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
pll25dac_din_o => pll25dac_din_o,
pll25dac_sclk_o => pll25dac_sclk_o,
pll25dac_sync_n_o => pll25dac_sync_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_in,
eeprom_sda_o => eeprom_sda_out,
eeprom_scl_i => eeprom_scl_in,
eeprom_scl_o => eeprom_scl_out,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
wb_slave_o => cnx_slave_out(c_WB_SLAVE_WRC),
wb_slave_i => cnx_slave_in(c_WB_SLAVE_WRC),
wrf_src_o => eth_rx_in,
wrf_src_i => eth_rx_out,
wrf_snk_o => eth_tx_in,
wrf_snk_i => eth_tx_out,
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o => tm_dac_wr,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
tm_clk_aux_locked_o => tm_clk_aux_locked,
pps_ext_i => pps_ext_in,
pps_p_o => pps,
pps_led_o => pps_led,
led_link_o => wr_led_link,
led_act_o => wr_led_act);
-- tri-state Carrier EEPROM
carrier_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
eeprom_sda_in <= carrier_sda_b;
carrier_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
eeprom_scl_in <= carrier_scl_b;
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- tri-state onewire access
onewire_b <= '0' when (onewire_oe = '1') else 'Z';
onewire_data <= onewire_b;
-- fmc i2c
fmc0_scl_b <= '0' when (fmc0_scl_out = '0') else 'Z';
fmc0_sda_b <= '0' when (fmc0_sda_out = '0') else 'Z';
fmc1_scl_b <= '0' when (fmc1_scl_out = '0') else 'Z';
fmc1_sda_b <= '0' when (fmc1_sda_out = '0') else 'Z';
-----------------------------------------------------------------------------
-- FMC TDC (SVEC slot #0)
-----------------------------------------------------------------------------
U_TDC_Core : fmc_tdc_wrapper
generic map (
g_simulation => f_int2bool(g_simulation),
g_with_direct_readout => TRUE)
port map (
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => rst_sys_62m5_n,
pll_sclk_o => fmc0_tdc_pll_sclk_o,
pll_sdi_o => fmc0_tdc_pll_sdi_o,
pll_cs_o => fmc0_tdc_pll_cs_n_o,
pll_dac_sync_o => fmc0_tdc_pll_dac_sync_n_o,
pll_sdo_i => fmc0_tdc_pll_sdo_i,
pll_status_i => fmc0_tdc_pll_status_i,
tdc_clk_125m_p_i => fmc0_tdc_125m_clk_p_i,
tdc_clk_125m_n_i => fmc0_tdc_125m_clk_n_i,
acam_refclk_p_i => fmc0_tdc_acam_refclk_p_i,
acam_refclk_n_i => fmc0_tdc_acam_refclk_n_i,
start_from_fpga_o => fmc0_tdc_start_from_fpga_o,
err_flag_i => fmc0_tdc_err_flag_i,
int_flag_i => fmc0_tdc_int_flag_i,
start_dis_o => fmc0_tdc_start_dis_o,
stop_dis_o => fmc0_tdc_stop_dis_o,
data_bus_io => fmc0_tdc_data_bus_io,
address_o => fmc0_tdc_address_o,
cs_n_o => fmc0_tdc_cs_n_o,
oe_n_o => fmc0_tdc_oe_n_o,
rd_n_o => fmc0_tdc_rd_n_o,
wr_n_o => fmc0_tdc_wr_n_o,
ef1_i => fmc0_tdc_ef1_i,
ef2_i => fmc0_tdc_ef2_i,
enable_inputs_o => fmc0_tdc_enable_inputs_o,
term_en_1_o => fmc0_tdc_term_en_1_o,
term_en_2_o => fmc0_tdc_term_en_2_o,
term_en_3_o => fmc0_tdc_term_en_3_o,
term_en_4_o => fmc0_tdc_term_en_4_o,
term_en_5_o => fmc0_tdc_term_en_5_o,
tdc_led_status_o => fmc0_tdc_led_status_o,
tdc_led_trig1_o => fmc0_tdc_led_trig1_o,
tdc_led_trig2_o => fmc0_tdc_led_trig2_o,
tdc_led_trig3_o => fmc0_tdc_led_trig3_o,
tdc_led_trig4_o => fmc0_tdc_led_trig4_o,
tdc_led_trig5_o => fmc0_tdc_led_trig5_o,
tdc_in_fpga_1_i => fmc0_tdc_in_fpga_1_i,
tdc_in_fpga_2_i => fmc0_tdc_in_fpga_2_i,
tdc_in_fpga_3_i => fmc0_tdc_in_fpga_3_i,
tdc_in_fpga_4_i => fmc0_tdc_in_fpga_4_i,
tdc_in_fpga_5_i => fmc0_tdc_in_fpga_5_i,
mezz_scl_i => fmc0_scl_b,
mezz_sda_i => fmc0_sda_b,
mezz_scl_o => fmc0_scl_out,
mezz_sda_o => fmc0_sda_out,
mezz_one_wire_b => fmc0_tdc_onewire_b,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_tai_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(0),
tm_clk_aux_locked_i => tm_clk_aux_locked(0),
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr(0),
direct_slave_i => fmc_dp_wb_out(0),
direct_slave_o => fmc_dp_wb_in(0),
slave_i => cnx_slave_in(c_WB_SLAVE_FMC0),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC0),
irq_o => fmc_host_irq(0),
clk_125m_tdc_o => fmc0_clk_125m);
-----------------------------------------------------------------------------
-- FMC FDELAY (SVEC slot #1)
-----------------------------------------------------------------------------
cmp_fd_tdc_start1 : IBUFDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => FALSE)
port map (
O => fmc1_fd_tdc_start,
I => fmc1_fd_tdc_start_p_i,
IB => fmc1_fd_tdc_start_n_i);
U_DDR_PLL1 : entity work.fd_ddr_pll
port map (
RST => ddr1_pll_reset,
LOCKED => ddr1_pll_locked,
CLK_IN1_P => fmc1_fd_clk_ref_p_i,
CLK_IN1_N => fmc1_fd_clk_ref_n_i,
CLK_OUT1 => fmc1_clk_125m,
CLK_OUT2 => fmc1_clk_125m_180);
ddr1_pll_reset <= not fmc1_fd_pll_status_i;
fmc1_fd_pll_status <= fmc1_fd_pll_status_i and ddr1_pll_locked;
U_FineDelay_Core1 : fine_delay_core
generic map (
g_with_wr_core => TRUE,
g_simulation => f_int2bool(g_simulation),
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_ref_0_i => fmc1_clk_125m,
clk_ref_180_i => fmc1_clk_125m_180,
clk_sys_i => clk_sys_62m5,
clk_dmtd_i => '0',
rst_n_i => rst_sys_62m5_n,
dcm_reset_o => open,
dcm_locked_i => ddr1_pll_locked,
trig_a_i => fmc1_fd_trig_a_i,
tdc_cal_pulse_o => fmc1_fd_tdc_cal_pulse_o,
tdc_start_i => fmc1_fd_tdc_start,
dmtd_fb_in_i => fmc1_fd_dmtd_fb_in_i,
dmtd_fb_out_i => fmc1_fd_dmtd_fb_out_i,
dmtd_samp_o => fmc1_fd_dmtd_clk_o,
led_trig_o => fmc1_fd_led_trig_o,
ext_rst_n_o => fmc1_fd_ext_rst_n_o,
pll_status_i => fmc1_fd_pll_status,
acam_d_o => fmc1_fd_tdc_data_out,
acam_d_i => fmc1_fd_tdc_data_in,
acam_d_oen_o => fmc1_fd_tdc_data_oe,
acam_emptyf_i => fmc1_fd_tdc_emptyf_i,
acam_alutrigger_o => fmc1_fd_tdc_alutrigger_o,
acam_wr_n_o => fmc1_fd_tdc_wr_n_o,
acam_rd_n_o => fmc1_fd_tdc_rd_n_o,
acam_start_dis_o => fmc1_fd_tdc_start_dis_o,
acam_stop_dis_o => fmc1_fd_tdc_stop_dis_o,
spi_cs_dac_n_o => fmc1_fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fmc1_fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fmc1_fd_spi_cs_gpio_n_o,
spi_sclk_o => fmc1_fd_spi_sclk_o,
spi_mosi_o => fmc1_fd_spi_mosi_o,
spi_miso_i => fmc1_fd_spi_miso_i,
delay_len_o => fmc1_fd_delay_len_o,
delay_val_o => fmc1_fd_delay_val_o,
delay_pulse_o => fmc1_fd_delay_pulse_o,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_utc_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(1),
tm_clk_aux_locked_i => tm_clk_aux_locked(1),
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr(1),
owr_en_o => fmc1_fd_owr_en,
owr_i => fmc1_fd_owr_in,
i2c_scl_oen_o => fmc1_scl_out,
i2c_scl_i => fmc1_fd_scl_in,
i2c_sda_oen_o => fmc1_sda_out,
i2c_sda_i => fmc1_fd_sda_in,
fmc_present_n_i => fmc1_prsntm2c_n_i,
wb_adr_i => fmc1_mux_wb_out.adr,
wb_dat_i => fmc1_mux_wb_out.dat,
wb_dat_o => fmc1_mux_wb_in.dat,
wb_sel_i => fmc1_mux_wb_out.sel,
wb_cyc_i => fmc1_mux_wb_out.cyc,
wb_stb_i => fmc1_mux_wb_out.stb,
wb_we_i => fmc1_mux_wb_out.we,
wb_ack_o => fmc1_mux_wb_in.ack,
wb_stall_o => fmc1_mux_wb_in.stall,
wb_irq_o => fmc_host_irq(1));
cmp_fmc1_wb_mux : xwb_crossbar
generic map (
g_num_masters => 2,
g_num_slaves => 1,
g_registered => TRUE,
g_address => c_FMC_MUX_ADDR,
g_mask => c_FMC_MUX_MASK)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i(0) => fmc_dp_wb_out(1),
slave_i(1) => cnx_slave_in(c_WB_SLAVE_FMC1),
slave_o(0) => fmc_dp_wb_in(1),
slave_o(1) => cnx_slave_out(c_WB_SLAVE_FMC1),
master_i(0) => fmc1_mux_wb_in,
master_o(0) => fmc1_mux_wb_out);
fmc1_mux_wb_in.err <= '0';
fmc1_mux_wb_in.rty <= '0';
-- tristate buffer for the TDC data bus:
fmc1_fd_tdc_d_b <= fmc1_fd_tdc_data_out when fmc1_fd_tdc_data_oe = '1' else (others => 'Z');
fmc1_fd_tdc_oe_n_o <= '1';
fmc1_fd_tdc_data_in <= fmc1_fd_tdc_d_b;
fmc1_fd_onewire_b <= '0' when fmc1_fd_owr_en = '1' else 'Z';
fmc1_fd_owr_in <= fmc1_fd_onewire_b;
fmc1_fd_scl_in <= fmc1_scl_b;
fmc1_fd_sda_in <= fmc1_sda_b;
-----------------------------------------------------------------------------
-- Carrier front panel LEDs and LEMOs
-----------------------------------------------------------------------------
cmp_led_controller : gc_bicolor_led_ctrl
generic map(
g_nb_column => 4,
g_nb_line => 2,
g_clk_freq => 62500000, -- in Hz
g_refresh_rate => 250 -- in Hz
)
port map(
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
led_intensity_i => "1100100", -- in %
led_state_i => svec_led,
column_o => fp_led_column_o,
line_o => fp_led_line_o,
line_oen_o => fp_led_line_oen_o);
-- LED 1
svec_led(1 downto 0) <= c_led_green when wr_led_link = '1' else c_led_red;
-- LED 2
svec_led(3 downto 2) <= c_led_green when tm_clk_aux_locked(0) = '1' else c_led_red;
-- LED 3
svec_led(5 downto 4) <= c_led_green when tm_time_valid = '1' else c_led_red;
-- LED 4
svec_led(7 downto 6) <= c_led_red_green when vme_access_led = '1' else c_led_off;
-- LED 5
svec_led(9 downto 8) <= c_led_red_green when wr_led_act = '1' else c_led_off;
-- LED 6
svec_led(11 downto 10) <= c_led_green when tm_clk_aux_locked(1) = '1' else c_led_red;
-- LED 7
svec_led(13 downto 12) <= c_led_off;
-- LED 8
svec_led(15 downto 14) <= c_led_green when pps_led = '1' else c_led_off;
-- Div by 2 reference clock to LEMO connector
process(clk_ref_125m)
begin
if rising_edge(clk_ref_125m) then
clk_ref_div2 <= not clk_ref_div2;
end if;
end process;
-- Front panel IO configuration
fp_gpio1_o <= pps;
fp_gpio2_o <= clk_ref_div2;
clk_ext_ref <= fp_gpio3_i;
pps_ext_in <= fp_gpio4_i;
fp_term_en_o <= (others => '0');
fp_gpio1_a2b_o <= '1';
fp_gpio2_a2b_o <= '1';
fp_gpio34_a2b_o <= '0';
end architecture arch;
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