Skip to content

GitLab

Commit 91be699a authored by Tristan Gingold's avatar Tristan Gingold
Browse files

hdl: add wrtd_ref_svec_adc_x2

parent 4513ccb9
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1821 additions and 0 deletions
hdl/syn/wrtd_ref_svec_adc_x2/Manifest.py 0 → 100644
View file @ 91be699a
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "wrtd_ref_svec_adc_x2"
syn_project = "wrtd_ref_svec_adc_x2.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
files = [
"buildinfo_pkg.vhd",
# fetchto + "/fmc-tdc/hdl/syn/svec/svec-tdc0.ucf",
# fetchto + "/fmc-tdc/hdl/syn/svec/svec-tdc1.ucf",
"wrtd_ref_svec_adc_x2.ucf",
]
modules = {
"local" : [
"../../top/wrtd_ref_svec_adc_x2",
],
}
#syn_pre_project_cmd = "make -C ../../../software/firmware"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'ddr4', 'ddr5', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/syn/wrtd_ref_svec_adc_x2/syn_extra_steps.tcl 0 → 100644
View file @ 91be699a
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/syn/wrtd_ref_svec_adc_x2/wrtd_ref_svec_adc_x2.ucf 0 → 100644
View file @ 91be699a
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
#===============================================================================
# IO Constraints
#===============================================================================
#----------------------------------------
# FMC slots
#----------------------------------------
# FMC0
NET "adc_ext_trigger_n_i[0]" LOC = "A15";
NET "adc_ext_trigger_p_i[0]" LOC = "B15";
NET "adc_dco_n_i[0]" LOC = "A16";
NET "adc_dco_p_i[0]" LOC = "C16";
NET "adc_fr_n_i[0]" LOC = "G21";
NET "adc_fr_p_i[0]" LOC = "H21";
NET "adc_outa_n_i[0]" LOC = "E17";
NET "adc_outa_p_i[0]" LOC = "F17";
NET "adc_outb_n_i[0]" LOC = "G16";
NET "adc_outb_p_i[0]" LOC = "H16";
NET "adc_outa_n_i[1]" LOC = "E19";
NET "adc_outa_p_i[1]" LOC = "F19";
NET "adc_outb_n_i[1]" LOC = "F18";
NET "adc_outb_p_i[1]" LOC = "G18";
NET "adc_outa_n_i[2]" LOC = "K21";
NET "adc_outa_p_i[2]" LOC = "L21";
NET "adc_outb_n_i[2]" LOC = "L20";
NET "adc_outb_p_i[2]" LOC = "M20";
NET "adc_outa_n_i[3]" LOC = "F22";
NET "adc_outa_p_i[3]" LOC = "G22";
NET "adc_outb_n_i[3]" LOC = "L19";
NET "adc_outb_p_i[3]" LOC = "M19";
NET "adc_spi_din_i[0]" LOC = "F11";
NET "adc_spi_dout_o[0]" LOC = "K11";
NET "adc_spi_sck_o[0]" LOC = "L11";
NET "adc_spi_cs_adc_n_o[0]" LOC = "J13";
NET "adc_spi_cs_dac1_n_o[0]" LOC = "H11";
NET "adc_spi_cs_dac2_n_o[0]" LOC = "G11";
NET "adc_spi_cs_dac3_n_o[0]" LOC = "J12";
NET "adc_spi_cs_dac4_n_o[0]" LOC = "H12";
NET "adc_gpio_dac_clr_n_o[0]" LOC = "H13";
NET "adc_gpio_led_acq_o[0]" LOC = "K12";
NET "adc_gpio_led_trig_o[0]" LOC = "L12";
NET "adc_gpio_ssr_ch1_o[0]" LOC = "L14";
NET "adc_gpio_ssr_ch1_o[1]" LOC = "K14";
NET "adc_gpio_ssr_ch1_o[2]" LOC = "L13";
NET "adc_gpio_ssr_ch1_o[3]" LOC = "E11";
NET "adc_gpio_ssr_ch1_o[4]" LOC = "G10";
NET "adc_gpio_ssr_ch1_o[5]" LOC = "F10";
NET "adc_gpio_ssr_ch1_o[6]" LOC = "F9";
NET "adc_gpio_ssr_ch2_o[0]" LOC = "F15";
NET "adc_gpio_ssr_ch2_o[1]" LOC = "F14";
NET "adc_gpio_ssr_ch2_o[2]" LOC = "F13";
NET "adc_gpio_ssr_ch2_o[3]" LOC = "E13";
NET "adc_gpio_ssr_ch2_o[4]" LOC = "G12";
NET "adc_gpio_ssr_ch2_o[5]" LOC = "M13";
NET "adc_gpio_ssr_ch2_o[6]" LOC = "F12";
NET "adc_gpio_ssr_ch3_o[0]" LOC = "F23";
NET "adc_gpio_ssr_ch3_o[1]" LOC = "E23";
NET "adc_gpio_ssr_ch3_o[2]" LOC = "F21";
NET "adc_gpio_ssr_ch3_o[3]" LOC = "E21";
NET "adc_gpio_ssr_ch3_o[4]" LOC = "G20";
NET "adc_gpio_ssr_ch3_o[5]" LOC = "F20";
NET "adc_gpio_ssr_ch3_o[6]" LOC = "E15";
NET "adc_gpio_ssr_ch4_o[0]" LOC = "J22";
NET "adc_gpio_ssr_ch4_o[1]" LOC = "H22";
NET "adc_gpio_ssr_ch4_o[2]" LOC = "E25";
NET "adc_gpio_ssr_ch4_o[3]" LOC = "D25";
NET "adc_gpio_ssr_ch4_o[4]" LOC = "D24";
NET "adc_gpio_ssr_ch4_o[5]" LOC = "B25";
NET "adc_gpio_ssr_ch4_o[6]" LOC = "C24";
NET "adc_gpio_si570_oe_o[0]" LOC = "A25";
NET "adc_si570_scl_b[0]" LOC = "H14";
NET "adc_si570_sda_b[0]" LOC = "J14";
NET "adc_one_wire_b[0]" LOC = "E9";
# FMC1
NET "adc_ext_trigger_n_i[1]" LOC = "AD16";
NET "adc_ext_trigger_p_i[1]" LOC = "AC16";
NET "adc_dco_n_i[1]" LOC = "AK17";
NET "adc_dco_p_i[1]" LOC = "AJ17";
NET "adc_fr_n_i[1]" LOC = "AH8";
NET "adc_fr_p_i[1]" LOC = "AG8";
NET "adc_outa_n_i[4]" LOC = "AA15";
NET "adc_outa_p_i[4]" LOC = "Y15";
NET "adc_outb_n_i[4]" LOC = "AA17";
NET "adc_outb_p_i[4]" LOC = "Y17";
NET "adc_outa_n_i[5]" LOC = "AC14";
NET "adc_outa_p_i[5]" LOC = "AB14";
NET "adc_outb_n_i[5]" LOC = "AD15";
NET "adc_outb_p_i[5]" LOC = "AC15";
NET "adc_outa_n_i[6]" LOC = "AA14";
NET "adc_outa_p_i[6]" LOC = "Y14";
NET "adc_outb_n_i[6]" LOC = "Y13";
NET "adc_outb_p_i[6]" LOC = "W14";
NET "adc_outa_n_i[7]" LOC = "AE12";
NET "adc_outa_p_i[7]" LOC = "AD12";
NET "adc_outb_n_i[7]" LOC = "AF11";
NET "adc_outb_p_i[7]" LOC = "AE11";
NET "adc_spi_din_i[1]" LOC = "AB17";
NET "adc_spi_dout_o[1]" LOC = "AA21";
NET "adc_spi_sck_o[1]" LOC = "Y21";
NET "adc_spi_cs_adc_n_o[1]" LOC = "W20";
NET "adc_spi_cs_dac1_n_o[1]" LOC = "W19";
NET "adc_spi_cs_dac2_n_o[1]" LOC = "Y19";
NET "adc_spi_cs_dac3_n_o[1]" LOC = "AA19";
NET "adc_spi_cs_dac4_n_o[1]" LOC = "AB19";
NET "adc_gpio_dac_clr_n_o[1]" LOC = "Y20";
NET "adc_gpio_led_acq_o[1]" LOC = "AC22";
NET "adc_gpio_led_trig_o[1]" LOC = "AA22";
NET "adc_gpio_ssr_ch1_o[7]" LOC = "AC19";
NET "adc_gpio_ssr_ch1_o[8]" LOC = "AD19";
NET "adc_gpio_ssr_ch1_o[9]" LOC = "AC20";
NET "adc_gpio_ssr_ch1_o[10]" LOC = "AD17";
NET "adc_gpio_ssr_ch1_o[11]" LOC = "AB21";
NET "adc_gpio_ssr_ch1_o[12]" LOC = "AC21";
NET "adc_gpio_ssr_ch1_o[13]" LOC = "AC24";
NET "adc_gpio_ssr_ch2_o[7]" LOC = "AE19";
NET "adc_gpio_ssr_ch2_o[8]" LOC = "AF23";
NET "adc_gpio_ssr_ch2_o[9]" LOC = "AE24";
NET "adc_gpio_ssr_ch2_o[10]" LOC = "AF24";
NET "adc_gpio_ssr_ch2_o[11]" LOC = "AD22";
NET "adc_gpio_ssr_ch2_o[12]" LOC = "AB20";
NET "adc_gpio_ssr_ch2_o[13]" LOC = "AE22";
NET "adc_gpio_ssr_ch3_o[7]" LOC = "AB12";
NET "adc_gpio_ssr_ch3_o[8]" LOC = "AC12";
NET "adc_gpio_ssr_ch3_o[9]" LOC = "AE15";
NET "adc_gpio_ssr_ch3_o[10]" LOC = "AF15";
NET "adc_gpio_ssr_ch3_o[11]" LOC = "Y16";
NET "adc_gpio_ssr_ch3_o[12]" LOC = "AB16";
NET "adc_gpio_ssr_ch3_o[13]" LOC = "AF19";
NET "adc_gpio_ssr_ch4_o[7]" LOC = "AC11";
NET "adc_gpio_ssr_ch4_o[8]" LOC = "AD11";
NET "adc_gpio_ssr_ch4_o[9]" LOC = "AE13";
NET "adc_gpio_ssr_ch4_o[10]" LOC = "AF13";
NET "adc_gpio_ssr_ch4_o[11]" LOC = "AJ15";
NET "adc_gpio_ssr_ch4_o[12]" LOC = "AD10";
NET "adc_gpio_ssr_ch4_o[13]" LOC = "AK15";
NET "adc_gpio_si570_oe_o[1]" LOC = "AE10";
NET "adc_si570_scl_b[1]" LOC = "AF21";
NET "adc_si570_sda_b[1]" LOC = "AE21";
NET "adc_one_wire_b[1]" LOC = "AD24";
# IO standards
NET "adc_ext_trigger_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_dco_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_fr_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_out?_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_spi_din_i[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_dout_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_sck_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_cs_adc_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_cs_dac?_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_dac_clr_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_led_acq_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_led_trig_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_ssr_ch?_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_si570_oe_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_si570_scl_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_si570_sda_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_one_wire_b[*]" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "gen_fmc_mezzanine[?].*/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 2.0 ns;
INST "gen_fmc_mezzanine[0].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X66Y189;
INST "gen_fmc_mezzanine[1].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X69Y2;
#----------------------------------------
# IOB exceptions
#----------------------------------------
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_i2c/U_Wrapped_I2C/*" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_onewire/*" IOB = FALSE;
#----------------------------------------
# Clocks
#----------------------------------------
NET "adc_dco_p_i[0]" TNM_NET = adc0_dco;
NET "adc_dco_n_i[0]" TNM_NET = adc0_dco;
TIMESPEC TS_adc0_dco = PERIOD "adc0_dco" 2.5 ns HIGH 50%;
NET "adc_dco_p_i[1]" TNM_NET = adc1_dco;
NET "adc_dco_n_i[1]" TNM_NET = adc1_dco;
TIMESPEC TS_adc1_dco = PERIOD "adc1_dco" 2.5 ns HIGH 50%;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "gen_fmc_mezzanine[0].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk;
NET "gen_fmc_mezzanine[1].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs1_clk;
TIMEGRP "adc0_sync_ffs" = "sync_ffs" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_ffs" = "sync_ffs" EXCEPT "fs1_clk";
#TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
#TIMESPEC TS_adc1_sync_ffs = FROM fs1_clk TO "adc1_sync_ffs" TIG;
TIMEGRP "adc0_sync_reg" = "sync_reg" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_reg" = "sync_reg" EXCEPT "fs1_clk";
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_adc1_sync_reg = FROM fs1_clk TO "adc1_sync_reg" 8ns DATAPATHONLY;
# No sync words used in FMC-ADC
#TIMESPEC TS_adc0_sync_word = FROM sync_word TO fs0_clk 30ns DATAPATHONLY;
#TIMESPEC TS_adc1_sync_word = FROM sync_word TO fs1_clk 30ns DATAPATHONLY;
hdl/top/wrtd_ref_svec_adc_x2/Manifest.py 0 → 100644
View file @ 91be699a
files = [
"wrtd_ref_svec_adc_x2.vhd",
"wrtd_adc_x2_host_map.vhd",
"wrtd_adc_x2_fmc_map.vhd",
]
fetchto = "../../../dependencies"
modules = {
"git" : [
"https://ohwr.org/project/svec.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/urv-core.git",
"https://ohwr.org/project/mock-turtle.git",
"https://ohwr.org/project/fmc-adc-100m14b4cha.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
hdl/top/wrtd_ref_svec_adc_x2/wrtd_adc_x2_fmc_map.cheby 0 → 100644
View file @ 91be699a
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: wrtd_adc_x2_fmc_map
bus: wb-32-be
description: WRTD ADC x2 dedicated peripheral map
size: 0x4000
x-hdl:
busgroup: True
pipeline: wr,rd
children:
- submap:
name: adc0_trigin
address: 0x0000
size: 0x1000
description: FMC ADC0 trigin
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: adc0_trigout
address: 0x1000
size: 0x1000
description: FMC ADC0 trigout
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: adc1_trigin
address: 0x2000
size: 0x1000
description: FMC ADC1 trigin
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: adc1_trigout
address: 0x3000
size: 0x1000
description: FMC ADC1 trigout
interface: wb-32-be
x-hdl:
busgroup: True
hdl/top/wrtd_ref_svec_adc_x2/wrtd_adc_x2_fmc_map.vhd 0 → 100644
View file @ 91be699a
-- Do not edit. Generated on Thu Feb 25 09:17:02 2021 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- --gen-hdl=wrtd_adc_x2_fmc_map.vhd -i wrtd_adc_x2_fmc_map.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity wrtd_adc_x2_fmc_map is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- FMC ADC0 trigin
adc0_trigin_i : in t_wishbone_master_in;
adc0_trigin_o : out t_wishbone_master_out;
-- FMC ADC0 trigout
adc0_trigout_i : in t_wishbone_master_in;
adc0_trigout_o : out t_wishbone_master_out;
-- FMC ADC1 trigin
adc1_trigin_i : in t_wishbone_master_in;
adc1_trigin_o : out t_wishbone_master_out;
-- FMC ADC1 trigout
adc1_trigout_i : in t_wishbone_master_in;
adc1_trigout_o : out t_wishbone_master_out
);
end wrtd_adc_x2_fmc_map;
architecture syn of wrtd_adc_x2_fmc_map is
signal adr_int : std_logic_vector(13 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal adc0_trigin_re : std_logic;
signal adc0_trigin_we : std_logic;
signal adc0_trigin_wt : std_logic;
signal adc0_trigin_rt : std_logic;
signal adc0_trigin_tr : std_logic;
signal adc0_trigin_wack : std_logic;
signal adc0_trigin_rack : std_logic;
signal adc0_trigout_re : std_logic;
signal adc0_trigout_we : std_logic;
signal adc0_trigout_wt : std_logic;
signal adc0_trigout_rt : std_logic;
signal adc0_trigout_tr : std_logic;
signal adc0_trigout_wack : std_logic;
signal adc0_trigout_rack : std_logic;
signal adc1_trigin_re : std_logic;
signal adc1_trigin_we : std_logic;
signal adc1_trigin_wt : std_logic;
signal adc1_trigin_rt : std_logic;
signal adc1_trigin_tr : std_logic;
signal adc1_trigin_wack : std_logic;
signal adc1_trigin_rack : std_logic;
signal adc1_trigout_re : std_logic;
signal adc1_trigout_we : std_logic;
signal adc1_trigout_wt : std_logic;
signal adc1_trigout_rt : std_logic;
signal adc1_trigout_tr : std_logic;
signal adc1_trigout_wack : std_logic;
signal adc1_trigout_rack : std_logic;
signal rd_req_d0 : std_logic;
signal rd_adr_d0 : std_logic_vector(13 downto 2);
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
signal wr_ack_d0 : std_logic;
begin
-- WB decode signals
adr_int <= wb_i.adr(13 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- pipelining for rd-in+rd-out+wr-in+wr-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_req_d0 <= '0';
rd_ack_int <= '0';
wr_req_d0 <= '0';
wr_ack_int <= '0';
else
rd_req_d0 <= rd_req_int;
rd_adr_d0 <= adr_int;
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
wr_ack_int <= wr_ack_d0;
end if;
end if;
end process;
-- Interface adc0_trigin
adc0_trigin_tr <= adc0_trigin_wt or adc0_trigin_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
adc0_trigin_rt <= '0';
adc0_trigin_wt <= '0';
else
adc0_trigin_rt <= (adc0_trigin_rt or adc0_trigin_re) and not adc0_trigin_rack;
adc0_trigin_wt <= (adc0_trigin_wt or adc0_trigin_we) and not adc0_trigin_wack;
end if;
end if;
end process;
adc0_trigin_o.cyc <= adc0_trigin_tr;
adc0_trigin_o.stb <= adc0_trigin_tr;
adc0_trigin_wack <= adc0_trigin_i.ack and adc0_trigin_wt;
adc0_trigin_rack <= adc0_trigin_i.ack and adc0_trigin_rt;
adc0_trigin_o.adr <= ((19 downto 0 => '0') & rd_adr_d0(11 downto 2)) & (1 downto 0 => '0');
adc0_trigin_o.sel <= wr_sel_d0;
adc0_trigin_o.we <= adc0_trigin_wt;
adc0_trigin_o.dat <= wr_dat_d0;
-- Interface adc0_trigout
adc0_trigout_tr <= adc0_trigout_wt or adc0_trigout_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
adc0_trigout_rt <= '0';
adc0_trigout_wt <= '0';
else
adc0_trigout_rt <= (adc0_trigout_rt or adc0_trigout_re) and not adc0_trigout_rack;
adc0_trigout_wt <= (adc0_trigout_wt or adc0_trigout_we) and not adc0_trigout_wack;
end if;
end if;
end process;
adc0_trigout_o.cyc <= adc0_trigout_tr;
adc0_trigout_o.stb <= adc0_trigout_tr;
adc0_trigout_wack <= adc0_trigout_i.ack and adc0_trigout_wt;
adc0_trigout_rack <= adc0_trigout_i.ack and adc0_trigout_rt;
adc0_trigout_o.adr <= ((19 downto 0 => '0') & rd_adr_d0(11 downto 2)) & (1 downto 0 => '0');
adc0_trigout_o.sel <= wr_sel_d0;
adc0_trigout_o.we <= adc0_trigout_wt;
adc0_trigout_o.dat <= wr_dat_d0;
-- Interface adc1_trigin
adc1_trigin_tr <= adc1_trigin_wt or adc1_trigin_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
adc1_trigin_rt <= '0';
adc1_trigin_wt <= '0';
else
adc1_trigin_rt <= (adc1_trigin_rt or adc1_trigin_re) and not adc1_trigin_rack;
adc1_trigin_wt <= (adc1_trigin_wt or adc1_trigin_we) and not adc1_trigin_wack;
end if;
end if;
end process;
adc1_trigin_o.cyc <= adc1_trigin_tr;
adc1_trigin_o.stb <= adc1_trigin_tr;
adc1_trigin_wack <= adc1_trigin_i.ack and adc1_trigin_wt;
adc1_trigin_rack <= adc1_trigin_i.ack and adc1_trigin_rt;
adc1_trigin_o.adr <= ((19 downto 0 => '0') & rd_adr_d0(11 downto 2)) & (1 downto 0 => '0');
adc1_trigin_o.sel <= wr_sel_d0;
adc1_trigin_o.we <= adc1_trigin_wt;
adc1_trigin_o.dat <= wr_dat_d0;
-- Interface adc1_trigout
adc1_trigout_tr <= adc1_trigout_wt or adc1_trigout_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
adc1_trigout_rt <= '0';
adc1_trigout_wt <= '0';
else
adc1_trigout_rt <= (adc1_trigout_rt or adc1_trigout_re) and not adc1_trigout_rack;
adc1_trigout_wt <= (adc1_trigout_wt or adc1_trigout_we) and not adc1_trigout_wack;
end if;
end if;
end process;
adc1_trigout_o.cyc <= adc1_trigout_tr;
adc1_trigout_o.stb <= adc1_trigout_tr;
adc1_trigout_wack <= adc1_trigout_i.ack and adc1_trigout_wt;
adc1_trigout_rack <= adc1_trigout_i.ack and adc1_trigout_rt;
adc1_trigout_o.adr <= ((19 downto 0 => '0') & rd_adr_d0(11 downto 2)) & (1 downto 0 => '0');
adc1_trigout_o.sel <= wr_sel_d0;
adc1_trigout_o.we <= adc1_trigout_wt;
adc1_trigout_o.dat <= wr_dat_d0;
-- Process for write requests.
process (rd_adr_d0, wr_req_d0, adc0_trigin_wack, adc0_trigout_wack, adc1_trigin_wack, adc1_trigout_wack) begin
adc0_trigin_we <= '0';
adc0_trigout_we <= '0';
adc1_trigin_we <= '0';
adc1_trigout_we <= '0';
case rd_adr_d0(13 downto 12) is
when "00" =>
-- Submap adc0_trigin
adc0_trigin_we <= wr_req_d0;
wr_ack_d0 <= adc0_trigin_wack;
when "01" =>
-- Submap adc0_trigout
adc0_trigout_we <= wr_req_d0;
wr_ack_d0 <= adc0_trigout_wack;
when "10" =>
-- Submap adc1_trigin
adc1_trigin_we <= wr_req_d0;
wr_ack_d0 <= adc1_trigin_wack;
when "11" =>
-- Submap adc1_trigout
adc1_trigout_we <= wr_req_d0;
wr_ack_d0 <= adc1_trigout_wack;
when others =>
wr_ack_d0 <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (rd_adr_d0, rd_req_d0, adc0_trigin_i.dat, adc0_trigin_rack, adc0_trigout_i.dat, adc0_trigout_rack, adc1_trigin_i.dat, adc1_trigin_rack, adc1_trigout_i.dat, adc1_trigout_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
adc0_trigin_re <= '0';
adc0_trigout_re <= '0';
adc1_trigin_re <= '0';
adc1_trigout_re <= '0';
case rd_adr_d0(13 downto 12) is
when "00" =>
-- Submap adc0_trigin
adc0_trigin_re <= rd_req_d0;
rd_dat_d0 <= adc0_trigin_i.dat;
rd_ack_d0 <= adc0_trigin_rack;
when "01" =>
-- Submap adc0_trigout
adc0_trigout_re <= rd_req_d0;
rd_dat_d0 <= adc0_trigout_i.dat;
rd_ack_d0 <= adc0_trigout_rack;
when "10" =>
-- Submap adc1_trigin
adc1_trigin_re <= rd_req_d0;
rd_dat_d0 <= adc1_trigin_i.dat;
rd_ack_d0 <= adc1_trigin_rack;
when "11" =>
-- Submap adc1_trigout
adc1_trigout_re <= rd_req_d0;
rd_dat_d0 <= adc1_trigout_i.dat;
rd_ack_d0 <= adc1_trigout_rack;
when others =>
rd_ack_d0 <= rd_req_d0;
end case;
end process;
end syn;
hdl/top/wrtd_ref_svec_adc_x2/wrtd_adc_x2_host_map.cheby 0 → 100644
View file @ 91be699a
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: wrtd_adc_x2_host_map
bus: wb-32-be
description: WRTD FMC-ADC-100M memory map
size: 0x40000
x-hdl:
busgroup: True
pipeline: wr,rd
children:
- submap:
name: metadata
address: 0x4000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
description: a ROM containing the application metadata
- submap:
name: adc0
address: 0x6000
size: 0x2000
description: FMC ADC Mezzanine slot 1
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: adc1
address: 0x8000
size: 0x2000
description: FMC ADC Mezzanine slot 2
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: mt
address: 0x20000
size: 0x20000
description: Mock-turtle
interface: wb-32-be
x-hdl:
busgroup: True
hdl/top/wrtd_ref_svec_adc_x2/wrtd_adc_x2_host_map.vhd 0 → 100644
View file @ 91be699a
-- Do not edit. Generated on Thu Feb 25 09:14:33 2021 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- --gen-hdl=wrtd_adc_x2_host_map.vhd -i wrtd_adc_x2_host_map.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity wrtd_adc_x2_host_map is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- a ROM containing the application metadata
metadata_i : in t_wishbone_master_in;
metadata_o : out t_wishbone_master_out;
-- FMC ADC Mezzanine slot 1
adc0_i : in t_wishbone_master_in;
adc0_o : out t_wishbone_master_out;
-- FMC ADC Mezzanine slot 2
adc1_i : in t_wishbone_master_in;
adc1_o : out t_wishbone_master_out;
-- Mock-turtle
mt_i : in t_wishbone_master_in;
mt_o : out t_wishbone_master_out
);
end wrtd_adc_x2_host_map;
architecture syn of wrtd_adc_x2_host_map is
signal adr_int : std_logic_vector(17 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_re : std_logic;
signal metadata_we : std_logic;
signal metadata_wt : std_logic;
signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal adc0_re : std_logic;
signal adc0_we : std_logic;
signal adc0_wt : std_logic;
signal adc0_rt : std_logic;
signal adc0_tr : std_logic;
signal adc0_wack : std_logic;
signal adc0_rack : std_logic;
signal adc1_re : std_logic;
signal adc1_we : std_logic;
signal adc1_wt : std_logic;
signal adc1_rt : std_logic;
signal adc1_tr : std_logic;
signal adc1_wack : std_logic;
signal adc1_rack : std_logic;
signal mt_re : std_logic;
signal mt_we : std_logic;
signal mt_wt : std_logic;
signal mt_rt : std_logic;
signal mt_tr : std_logic;
signal mt_wack : std_logic;
signal mt_rack : std_logic;
signal rd_req_d0 : std_logic;
signal rd_adr_d0 : std_logic_vector(17 downto 2);
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
signal wr_ack_d0 : std_logic;
begin
-- WB decode signals
adr_int <= wb_i.adr(17 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- pipelining for rd-in+rd-out+wr-in+wr-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_req_d0 <= '0';
rd_ack_int <= '0';
wr_req_d0 <= '0';
wr_ack_int <= '0';
else
rd_req_d0 <= rd_req_int;
rd_adr_d0 <= adr_int;
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
wr_ack_int <= wr_ack_d0;
end if;
end if;
end process;
-- Interface metadata
metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
metadata_wt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
metadata_wt <= (metadata_wt or metadata_we) and not metadata_wack;
end if;
end if;
end process;
metadata_o.cyc <= metadata_tr;
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & rd_adr_d0(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= wr_sel_d0;
metadata_o.we <= metadata_wt;
metadata_o.dat <= wr_dat_d0;
-- Interface adc0
adc0_tr <= adc0_wt or adc0_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
adc0_rt <= '0';
adc0_wt <= '0';
else
adc0_rt <= (adc0_rt or adc0_re) and not adc0_rack;
adc0_wt <= (adc0_wt or adc0_we) and not adc0_wack;
end if;
end if;
end process;
adc0_o.cyc <= adc0_tr;
adc0_o.stb <= adc0_tr;
adc0_wack <= adc0_i.ack and adc0_wt;
adc0_rack <= adc0_i.ack and adc0_rt;
adc0_o.adr <= ((18 downto 0 => '0') & rd_adr_d0(12 downto 2)) & (1 downto 0 => '0');
adc0_o.sel <= wr_sel_d0;
adc0_o.we <= adc0_wt;
adc0_o.dat <= wr_dat_d0;
-- Interface adc1
adc1_tr <= adc1_wt or adc1_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
adc1_rt <= '0';
adc1_wt <= '0';
else
adc1_rt <= (adc1_rt or adc1_re) and not adc1_rack;
adc1_wt <= (adc1_wt or adc1_we) and not adc1_wack;
end if;
end if;
end process;
adc1_o.cyc <= adc1_tr;
adc1_o.stb <= adc1_tr;
adc1_wack <= adc1_i.ack and adc1_wt;
adc1_rack <= adc1_i.ack and adc1_rt;
adc1_o.adr <= ((18 downto 0 => '0') & rd_adr_d0(12 downto 2)) & (1 downto 0 => '0');
adc1_o.sel <= wr_sel_d0;
adc1_o.we <= adc1_wt;
adc1_o.dat <= wr_dat_d0;
-- Interface mt
mt_tr <= mt_wt or mt_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
mt_rt <= '0';
mt_wt <= '0';
else
mt_rt <= (mt_rt or mt_re) and not mt_rack;
mt_wt <= (mt_wt or mt_we) and not mt_wack;
end if;
end if;
end process;
mt_o.cyc <= mt_tr;
mt_o.stb <= mt_tr;
mt_wack <= mt_i.ack and mt_wt;
mt_rack <= mt_i.ack and mt_rt;
mt_o.adr <= ((14 downto 0 => '0') & rd_adr_d0(16 downto 2)) & (1 downto 0 => '0');
mt_o.sel <= wr_sel_d0;
mt_o.we <= mt_wt;
mt_o.dat <= wr_dat_d0;
-- Process for write requests.
process (rd_adr_d0, wr_req_d0, metadata_wack, adc0_wack, adc1_wack, mt_wack) begin
metadata_we <= '0';
adc0_we <= '0';
adc1_we <= '0';
mt_we <= '0';
case rd_adr_d0(17 downto 17) is
when "0" =>
case rd_adr_d0(16 downto 13) is
when "0010" =>
-- Submap metadata
metadata_we <= wr_req_d0;
wr_ack_d0 <= metadata_wack;
when "0011" =>
-- Submap adc0
adc0_we <= wr_req_d0;
wr_ack_d0 <= adc0_wack;
when "0100" =>
-- Submap adc1
adc1_we <= wr_req_d0;
wr_ack_d0 <= adc1_wack;
when others =>
wr_ack_d0 <= wr_req_d0;
end case;
when "1" =>
-- Submap mt
mt_we <= wr_req_d0;
wr_ack_d0 <= mt_wack;
when others =>
wr_ack_d0 <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (rd_adr_d0, rd_req_d0, metadata_i.dat, metadata_rack, adc0_i.dat, adc0_rack, adc1_i.dat, adc1_rack, mt_i.dat, mt_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
metadata_re <= '0';
adc0_re <= '0';
adc1_re <= '0';
mt_re <= '0';
case rd_adr_d0(17 downto 17) is
when "0" =>
case rd_adr_d0(16 downto 13) is
when "0010" =>
-- Submap metadata
metadata_re <= rd_req_d0;
rd_dat_d0 <= metadata_i.dat;
rd_ack_d0 <= metadata_rack;
when "0011" =>
-- Submap adc0
adc0_re <= rd_req_d0;
rd_dat_d0 <= adc0_i.dat;
rd_ack_d0 <= adc0_rack;
when "0100" =>
-- Submap adc1
adc1_re <= rd_req_d0;
rd_dat_d0 <= adc1_i.dat;
rd_ack_d0 <= adc1_rack;
when others =>
rd_ack_d0 <= rd_req_d0;
end case;
when "1" =>
-- Submap mt
mt_re <= rd_req_d0;
rd_dat_d0 <= mt_i.dat;
rd_ack_d0 <= mt_rack;
when others =>
rd_ack_d0 <= rd_req_d0;
end case;
end process;
end syn;
hdl/top/wrtd_ref_svec_adc_x2/wrtd_ref_svec_adc_x2.vhd 0 → 100644
View file @ 91be699a
This diff is collapsed.
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment