Skip to content

W
White Rabbit Trigger Distribution
Commit 0f59185c authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

Merge branch 'proposed_master'

parents dbd72902 f277c6a6
Expand all Show whitespace changes
Inline Side-by-side
Showing with 7573 additions and 751 deletions
.gitmodules
View file @ 0f59185c
......@@ -4,9 +4,6 @@
[submodule "dependencies/fine-delay"]
path = dependencies/fmc-delay-1ns-8cha
url = https://ohwr.org/project/fmc-delay-1ns-8cha.git
[submodule "dependencies/fmc-tdc"]
path = dependencies/fmc-tdc-1ns-5cha-gw
url = https://ohwr.org/project/fmc-tdc-1ns-5cha-gw.git
[submodule "dependencies/vme64x-core"]
path = dependencies/vme64x-core
url = https://ohwr.org/project/vme64x-core.git
......@@ -19,9 +16,6 @@
[submodule "dependencies/urv-core"]
path = dependencies/urv-core
url = https://ohwr.org/project/urv-core.git
[submodule "dependencies/fmc-adc-100m14b4cha-gw"]
path = dependencies/fmc-adc-100m14b4cha-gw
url = https://ohwr.org/project/fmc-adc-100m14b4cha-gw.git
[submodule "dependencies/ddr3-sp6-core"]
path = dependencies/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
......@@ -34,3 +28,11 @@
[submodule "dependencies/svec"]
path = dependencies/svec
url = https://ohwr.org/project/svec.git
[submodule "dependencies/fmc-tdc"]
path = dependencies/fmc-tdc
url = https://ohwr.org/project/fmc-tdc.git
branch = develop
[submodule "dependencies/fmc-adc-100m14b4cha"]
path = dependencies/fmc-adc-100m14b4cha
url = https://ohwr.org/project/fmc-adc-100m14b4cha.git
branch = master
CHANGELOG.md
View file @ 0f59185c
......@@ -5,6 +5,12 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
## [Unreleased]
### Added
- udev rules for proper node initialisation
### Changed
- Better python packaging, including wrtd-tool
### Fixed
- Building of drivers in newer (post 4.19) Linux kernels
## [1.0.1] - 2021-02-10
### Fixed
......
fmc-adc-100m14b4cha @ b06636f5
Subproject commit b06636f542b2a69ca461db1faee767814ac27714
fmc-adc-100m14b4cha-gw @ dabad887
Subproject commit dabad887078b575d7d4eff8ab570e29c299853ef
fmc-delay-1ns-8cha @ 2bdeecbd
Subproject commit dae483e3ca0ee971861ef7a5455a2dd7b3c610a0
Subproject commit 2bdeecbd4f349f3e72c42373de84432286ae3306
fmc-tdc @ 099aebec
Subproject commit 099aebecd2b6237dd49dfee6f67cb3c072b7bd96
fmc-tdc-1ns-5cha-gw @ e66d3b45
Subproject commit e66d3b45345e1c518697ad5574f80cb825527465
general-cores @ 7d76d2b6
Subproject commit 284373b7ea1db559dd323634dd34a8dba1811c12
Subproject commit 7d76d2b6503cd3f129fd4bc3797b6abfefb752c5
spec @ 483c3fc7
Subproject commit e52fec7c961efbc3f66419fc8eb2d16accef0e2a
Subproject commit 483c3fc7306cec24a5e770dd548820c8cc3147f7
svec @ 5c8b5729
Subproject commit cf6b2894a6c0d3e0b755f73f1310a58074770eda
Subproject commit 5c8b5729b24364698839f3ff1762f9944a4b4bf8
wr-cores @ 3884a655
Subproject commit 3dcac4483417a159f0b9495adab0c15b7b45692b
Subproject commit 3884a65545907de3a0d41d549a4be9e6cccb4916
doc/conf.py
View file @ 0f59185c
......@@ -59,7 +59,7 @@ master_doc = 'index'
# General information about the project.
project = u'White Rabbit Trigger Distribution'
copyright = u'2019, CERN, documentation released under CC-BY-SA-4.0'
author = u'Dimitris Lampridis <dimitris.lampridis@cern.ch'
author = u'Dimitris Lampridis <dimitris.lampridis@cern.ch>'
# The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the
......@@ -75,7 +75,7 @@ release = u'1.0'
#
# This is also used if you do content translation via gettext catalogs.
# Usually you set "language" from the command line for these cases.
language = None
# language = None
# There are two options for replacing |today|: either, you set today to some
# non-false value, then it is used:
......
doc/devel.rst
View file @ 0f59185c
......@@ -232,7 +232,7 @@ functions. These include:
+ :cpp:func:`wr_link_up`
+ :cpp:func:`wr_time_ready`
+ :cpp:func:`wr_enable_lock`
+ :cpp:func:`wr_time_locked`
+ :cpp:func:`wr_aux_locked`
+ :cpp:func:`wr_sync_timeout`
* :ref:`fw_api_event_in`
......@@ -264,7 +264,7 @@ done.
.. doxygenfunction:: wr_link_up
.. doxygenfunction:: wr_time_ready
.. doxygenfunction:: wr_enable_lock
.. doxygenfunction:: wr_time_locked
.. doxygenfunction:: wr_aux_locked
.. doxygenfunction:: wr_sync_timeout
Event I/O
......
doc/installation.rst
View file @ 0f59185c
......@@ -14,6 +14,8 @@ Installation
procedures have been finalised and tested, the contents of the wiki page will be merged
here.
.. _permissions:
Permissions
===========
......
doc/introduction.rst
View file @ 0f59185c
......@@ -98,7 +98,7 @@ design WRTD to be as close to LXI as possible. In particular:
.. hint:: Do not worry if you do not understand some of the terminology yet. It will be explained in
:numref:`basic_concepts`.
In the future, and with `White Rabbit being standardised within the next release of IEEE-1588
In the future, and with `White Rabbit standardised within IEEE-1588-2019
<https://www.ohwr.org/project/wr-std/wikis/home>`_, it is foreseen to try to merge WRTD with
IVI/LXI. A possible way to do this would be to add a new IVI specification, similar to IVI-3.15,
describing the API to control WRTD-enabled devices. This API would be an extension, allowing any
......
doc/ref_nodes.rst
View file @ 0f59185c
......@@ -15,9 +15,14 @@ Currently these include:
WRTD.
#. :ref:`svec_ref_tdc_fd`: A pulse-in/pulse-out WRTD Node in VME format, for generic trigger
distribution applications.
#. :ref:`svec_ref_tdc_x2`: A pulse-in WRTD Node in VME format.
#. :ref:`svec_ref_fd_x2`: A pulse-out WRTD Node in VME format.
.. toctree::
:hidden:
ref_spec_fmc_adc
ref_svec_tdc_fd
ref_svec_tdc_x2
ref_svec_fd_x2
ref_svec_adc_x2
doc/ref_svec_adc_x2.rst 0 → 100644
View file @ 0f59185c
.. Copyright (c) 2019 CERN (home.cern)
SPDX-License-Identifier: CC-BY-SA-4.0
.. _svec_ref_adc_x2:
SVEC-based ADC x 2
==================
This is a WRTD :ref:`node` based on the `Simple VME FMC Carrier (SVEC)
<https://www.ohwr.org/project/svec/wikis/home>`_ and the `FMC ADC 100M 14b 4cha (FMC-ADC)
<https://www.ohwr.org/project/fmc-adc-100m14b4cha/wikis/home>`_.
This :ref:`node` provides the possibility to generate WRTD :ref:`Messages <message>` based on
trigger events of the FMC-ADC, as well as to trigger the FMC-ADC from incoming WRTD :ref:`Messages
<message>`.
The node has 10 :ref:`Local Input Channels <local_channel>`. Channels 1 to 4
are mapped to the internal trigger of adc #1, channel 5 to the external trigger
input of adc #1, channels 6 to 9 to the intern triggers of adc #2 and
channel 10 to the external trigger input of adc #2.
doc/ref_svec_fd_x2.rst 0 → 100644
View file @ 0f59185c
.. Copyright (c) 2019 CERN (home.cern)
SPDX-License-Identifier: CC-BY-SA-4.0
.. _svec_ref_fd_x2:
SVEC-based FD x 2
=================
This is a WRTD :ref:`node` based on the `Simple VME FMC Carrier (SVEC)
<https://www.ohwr.org/project/svec/wikis/home>`_ and the `FMC Fine Delay generator
(FMC-FD) <https://www.ohwr.org/project/fmc-delay-1ns-8cha/wikis/home>`_.
The basic principle of this :ref:`node` is simple: the :ref:`node`
also receives WRTD :ref:`Messages <message>` which are then used to
generate pulses at a predefined moment on one of the FMC-FD outputs.
Architecture and performances are similar to :ref:`svec_ref_tdc_fd`.
The node has 10 :ref:`Local Output Channels <local_channel>`, they are
mapped to the five inputs of each FMC-FD.
doc/ref_svec_tdc_fd.rst
View file @ 0f59185c
......@@ -25,7 +25,7 @@ SVEC-based TDC+FD
+----------------------------------------+------------+------------+
| Average input to Message latency | 20μs | N.A. |
+----------------------------------------+------------+------------+
| Average Message to output latency | N.A. | 40μs |
| Average Message to output latency | N.A. | 20μs |
+----------------------------------------+------------+------------+
| Can receive Messages over WR | NO | YES |
+----------------------------------------+------------+------------+
......@@ -34,8 +34,8 @@ SVEC-based TDC+FD
This is a WRTD :ref:`node` based on the `Simple VME FMC Carrier (SVEC)
<https://www.ohwr.org/project/svec/wikis/home>`_, the `FMC Time to Digital Converter (FMC-TDC)
<https://www.ohwr.org/project/fmc-tdc-1ns-5cha-hw/wikis/home>`_ and the `FMC Fine Delay generator
(FMC-FD) <https://www.ohwr.org/project/fmc-delay-1ns-8cha/wikis/home>`_.
<https://www.ohwr.org/project/fmc-tdc/wikis/home>`_ and the `FMC Fine Delay generator (FMC-FD)
<https://www.ohwr.org/project/fmc-delay-1ns-8cha/wikis/home>`_.
.. important:: The FMC-TDC should always be attached to "FMC Slot 1" of the SVEC, and the FMC-FD
should always be attached to "FMC Slot 2". It is not necessary though to have both
......
doc/ref_svec_tdc_x2.rst 0 → 100644
View file @ 0f59185c
.. Copyright (c) 2019 CERN (home.cern)
SPDX-License-Identifier: CC-BY-SA-4.0
.. _svec_ref_tdc_x2:
SVEC-based TDC x 2
==================
This is a WRTD :ref:`node` based on the `Simple VME FMC Carrier (SVEC)
<https://www.ohwr.org/project/svec/wikis/home>`_ and the `FMC Time to Digital Converter (FMC-TDC)
<https://www.ohwr.org/project/fmc-tdc/wikis/home>`_.
The basic principle of this :ref:`node` is simple: it takes in
external pulses on its FMC-TDC inputs, timestamps them using WR time
and converts them to WRTD :ref:`Messages <message>`, to be sent over
the WR network.
Architecture and performances are similar to :ref:`svec_ref_tdc_fd`.
The node has 10 :ref:`Local Input Channels <local_channel>`, they are mapped
to the five inputs of each FMC-TDC.
doc/requirements.txt
View file @ 0f59185c
docutils==0.14
Sphinx==1.8.5
sphinx_rtd_theme
breathe==4.11.0
recommonmark==0.5.0
decorator==4.4.0
docutils==0.17.1
Sphinx==5.1.1
sphinx_rtd_theme==1.0.0
breathe==4.34.0
recommonmark==0.7.1
decorator==5.1.1
doc/usage_clib.rst
View file @ 0f59185c
......@@ -92,6 +92,40 @@ Functions
examples. However, in a real application, users should always check the status code of every call
to a WRTD function, like in :numref:`lst-get_error`.
.. hint::
If you want to be sure that the buffer that you pass to :cpp:func:`wrtd_get_error`
is large enough, without having to resort to querying like in :numref:`lst-get_error`, you can
always allocate a buffer of :c:macro:`WRTD_ERR_MSG_BUF_SIZE`. WRTD guarantees that all error
messages shall not exceed this size.
.. doxygendefine:: WRTD_ERR_MSG_BUF_SIZE
.. code-block:: c
:caption: Retrieving the error message with a pre-defined buffer size
#include <libwrtd.h>
int main(void) {
wrtd_dev *wrtd;
wrtd_status status;
char err_msg[WRTD_ERR_MSG_BUF_SIZE];
status = wrtd_init(1, false, NULL, &wrtd);
status = wrtd_get_attr_bool(wrtd, WRTD_GLOBAL_REP_CAP_ID,
WRTD_ATTR_EVENT_LOG_EMPTY);
if (status != WRTD_SUCCESS) {
/* retrieve the error code and message */
wrtd_get_error(wrtd, &err_code, WRTD_ERR_MSG_BUF_SIZE, err_msg)
printf("ERROR: %d, %s\n", err_code, err_msg);
return status;
}
wrtd_close(wrtd);
return 0;
}
.. _api_init:
Initialisation API
......@@ -257,7 +291,7 @@ Functions
/* get the delay configured for "rule1" */
status = wrtd_get_attr_tstamp(wrtd, "rule1",
WRTD_ATTR_RULE_DELAY, &ts");
WRTD_ATTR_RULE_DELAY, &ts);
wrtd_close(wrtd);
}
......@@ -295,6 +329,7 @@ The Event Logging API provides functions for accessing the :ref:`event_log`.
int main(void) {
wrtd_dev *wrtd;
wrtd_status status;
char *log_msg;
int buf_size;
......@@ -332,6 +367,7 @@ The Event Logging API provides functions for accessing the :ref:`event_log`.
int main(void) {
wrtd_dev *wrtd;
wrtd_status status;
char log_msg[WRTD_LOG_ENTRY_SIZE];
status = wrtd_init(1, false, NULL, &wrtd);
......@@ -368,6 +404,7 @@ Configuration of an Alarm happens by setting the relevant :ref:`Attributes <attr
int i, count;
char rep_cap_id[16];
wrtd_dev *wrtd;
wrtd_status status;
status = wrtd_init(1, false, NULL, &wrtd);
......@@ -427,6 +464,7 @@ Configuration of a Rule happens by setting the relevant :ref:`Attributes <attrib
int i, count;
char rep_cap_id[16];
wrtd_dev *wrtd;
wrtd_status status;
status = wrtd_init(1, false, NULL, &wrtd);
......@@ -487,7 +525,7 @@ Configuration of a Rule happens by setting the relevant :ref:`Attributes <attrib
/* Enable rule */
status = wrtd_set_attr_bool(wrtd, "rule1",
WRTD_ATTR_RULE_ENABLED, True);
WRTD_ATTR_RULE_ENABLED, true);
wrtd_close(wrtd);
......@@ -516,6 +554,7 @@ relevant :ref:`Attributes <attribute>` via the :ref:`api_attr`.
int i, count, major, minor;
char rep_cap_id[16];
wrtd_dev *wrtd;
wrtd_status status;
status = wrtd_init(1, false, NULL, &wrtd);
......
doc/usage_pywrap.rst
View file @ 0f59185c
......@@ -42,7 +42,7 @@ In order to retrieve the ID of the :ref:`node`, the :py:class:`PyWrtd` class pro
methods :py:meth:`PyWrtd.PyWrtd.get_node_count` and :py:meth:`PyWrtd.PyWrtd.get_node_id` that can be
used before you instantiate the :py:class:`PyWrtd` object.
If the ID is wrong or if the user does not have the correct :ref:`permissions <permissions>` to
If the ID is wrong or if the user does not have the correct :ref:`permissions` to
access it, WRTD will return :cpp:enumerator:`WRTD_ERROR_RESOURCE_UNKNOWN`.
.. code-block:: python
......
doc/usage_tools.rst
View file @ 0f59185c
......@@ -6,13 +6,11 @@
Tools
=====
.. module:: PyWrtd
WRTD provides a comand-line, Python based tool (:ref:`wrtd_tool`) for accessing a :ref:`node`.
.. hint::
Please make sure that you run the tool wih the proper :ref:`permissions <permissions>`.
Please make sure that you run the tool wih the proper :ref:`permissions`.
For details on how to install the tool (and their dependencies), please refer to
:numref:`installation`.
......@@ -65,6 +63,7 @@ A list of the available commands can be retrieved by passing the ``-h`` option t
disable-alarm Disable an Alarm
disable-all-alarms Disable all Alarms
alarm-info Display information about an Alarm
cli Command line interface
Each command has its own built-in help system as well, which can be invoked by selecting a command
and passing the ``-h`` option after the command:
......
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
View file @ 0f59185c
......@@ -120,7 +120,7 @@ INST "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X68Y
#----------------------------------------
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_onewire/i_readout/*" IOB = FALSE;
#----------------------------------------
# Clocks
......
hdl/syn/wrtd_ref_svec_adc_x2/Manifest.py 0 → 100644
View file @ 0f59185c
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "wrtd_ref_svec_adc_x2"
syn_project = "wrtd_ref_svec_adc_x2.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
files = [
"buildinfo_pkg.vhd",
# fetchto + "/fmc-tdc/hdl/syn/svec/svec-tdc0.ucf",
# fetchto + "/fmc-tdc/hdl/syn/svec/svec-tdc1.ucf",
"wrtd_ref_svec_adc_x2.ucf",
]
modules = {
"local" : [
"../../top/wrtd_ref_svec_adc_x2",
],
}
#syn_pre_project_cmd = "make -C ../../../software/firmware"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'ddr4', 'ddr5', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/syn/wrtd_ref_svec_adc_x2/syn_extra_steps.tcl 0 → 100644
View file @ 0f59185c
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/syn/wrtd_ref_svec_adc_x2/wrtd_ref_svec_adc_x2.ucf 0 → 100644
View file @ 0f59185c
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
#===============================================================================
# IO Constraints
#===============================================================================
#----------------------------------------
# FMC slots
#----------------------------------------
# FMC0
NET "adc_ext_trigger_n_i[0]" LOC = "A15";
NET "adc_ext_trigger_p_i[0]" LOC = "B15";
NET "adc_dco_n_i[0]" LOC = "A16";
NET "adc_dco_p_i[0]" LOC = "C16";
NET "adc_fr_n_i[0]" LOC = "G21";
NET "adc_fr_p_i[0]" LOC = "H21";
NET "adc_outa_n_i[0]" LOC = "E17";
NET "adc_outa_p_i[0]" LOC = "F17";
NET "adc_outb_n_i[0]" LOC = "G16";
NET "adc_outb_p_i[0]" LOC = "H16";
NET "adc_outa_n_i[1]" LOC = "E19";
NET "adc_outa_p_i[1]" LOC = "F19";
NET "adc_outb_n_i[1]" LOC = "F18";
NET "adc_outb_p_i[1]" LOC = "G18";
NET "adc_outa_n_i[2]" LOC = "K21";
NET "adc_outa_p_i[2]" LOC = "L21";
NET "adc_outb_n_i[2]" LOC = "L20";
NET "adc_outb_p_i[2]" LOC = "M20";
NET "adc_outa_n_i[3]" LOC = "F22";
NET "adc_outa_p_i[3]" LOC = "G22";
NET "adc_outb_n_i[3]" LOC = "L19";
NET "adc_outb_p_i[3]" LOC = "M19";
NET "adc_spi_din_i[0]" LOC = "F11";
NET "adc_spi_dout_o[0]" LOC = "K11";
NET "adc_spi_sck_o[0]" LOC = "L11";
NET "adc_spi_cs_adc_n_o[0]" LOC = "J13";
NET "adc_spi_cs_dac1_n_o[0]" LOC = "H11";
NET "adc_spi_cs_dac2_n_o[0]" LOC = "G11";
NET "adc_spi_cs_dac3_n_o[0]" LOC = "J12";
NET "adc_spi_cs_dac4_n_o[0]" LOC = "H12";
NET "adc_gpio_dac_clr_n_o[0]" LOC = "H13";
NET "adc_gpio_led_acq_o[0]" LOC = "K12";
NET "adc_gpio_led_trig_o[0]" LOC = "L12";
NET "adc_gpio_ssr_ch1_o[0]" LOC = "L14";
NET "adc_gpio_ssr_ch1_o[1]" LOC = "K14";
NET "adc_gpio_ssr_ch1_o[2]" LOC = "L13";
NET "adc_gpio_ssr_ch1_o[3]" LOC = "E11";
NET "adc_gpio_ssr_ch1_o[4]" LOC = "G10";
NET "adc_gpio_ssr_ch1_o[5]" LOC = "F10";
NET "adc_gpio_ssr_ch1_o[6]" LOC = "F9";
NET "adc_gpio_ssr_ch2_o[0]" LOC = "F15";
NET "adc_gpio_ssr_ch2_o[1]" LOC = "F14";
NET "adc_gpio_ssr_ch2_o[2]" LOC = "F13";
NET "adc_gpio_ssr_ch2_o[3]" LOC = "E13";
NET "adc_gpio_ssr_ch2_o[4]" LOC = "G12";
NET "adc_gpio_ssr_ch2_o[5]" LOC = "M13";
NET "adc_gpio_ssr_ch2_o[6]" LOC = "F12";
NET "adc_gpio_ssr_ch3_o[0]" LOC = "F23";
NET "adc_gpio_ssr_ch3_o[1]" LOC = "E23";
NET "adc_gpio_ssr_ch3_o[2]" LOC = "F21";
NET "adc_gpio_ssr_ch3_o[3]" LOC = "E21";
NET "adc_gpio_ssr_ch3_o[4]" LOC = "G20";
NET "adc_gpio_ssr_ch3_o[5]" LOC = "F20";
NET "adc_gpio_ssr_ch3_o[6]" LOC = "E15";
NET "adc_gpio_ssr_ch4_o[0]" LOC = "J22";
NET "adc_gpio_ssr_ch4_o[1]" LOC = "H22";
NET "adc_gpio_ssr_ch4_o[2]" LOC = "E25";
NET "adc_gpio_ssr_ch4_o[3]" LOC = "D25";
NET "adc_gpio_ssr_ch4_o[4]" LOC = "D24";
NET "adc_gpio_ssr_ch4_o[5]" LOC = "B25";
NET "adc_gpio_ssr_ch4_o[6]" LOC = "C24";
NET "adc_gpio_si570_oe_o[0]" LOC = "A25";
NET "adc_si570_scl_b[0]" LOC = "H14";
NET "adc_si570_sda_b[0]" LOC = "J14";
NET "adc_one_wire_b[0]" LOC = "E9";
# FMC1
NET "adc_ext_trigger_n_i[1]" LOC = "AD16";
NET "adc_ext_trigger_p_i[1]" LOC = "AC16";
NET "adc_dco_n_i[1]" LOC = "AK17";
NET "adc_dco_p_i[1]" LOC = "AJ17";
NET "adc_fr_n_i[1]" LOC = "AH8";
NET "adc_fr_p_i[1]" LOC = "AG8";
NET "adc_outa_n_i[4]" LOC = "AA15";
NET "adc_outa_p_i[4]" LOC = "Y15";
NET "adc_outb_n_i[4]" LOC = "AA17";
NET "adc_outb_p_i[4]" LOC = "Y17";
NET "adc_outa_n_i[5]" LOC = "AC14";
NET "adc_outa_p_i[5]" LOC = "AB14";
NET "adc_outb_n_i[5]" LOC = "AD15";
NET "adc_outb_p_i[5]" LOC = "AC15";
NET "adc_outa_n_i[6]" LOC = "AA14";
NET "adc_outa_p_i[6]" LOC = "Y14";
NET "adc_outb_n_i[6]" LOC = "Y13";
NET "adc_outb_p_i[6]" LOC = "W14";
NET "adc_outa_n_i[7]" LOC = "AE12";
NET "adc_outa_p_i[7]" LOC = "AD12";
NET "adc_outb_n_i[7]" LOC = "AF11";
NET "adc_outb_p_i[7]" LOC = "AE11";
NET "adc_spi_din_i[1]" LOC = "AB17";
NET "adc_spi_dout_o[1]" LOC = "AA21";
NET "adc_spi_sck_o[1]" LOC = "Y21";
NET "adc_spi_cs_adc_n_o[1]" LOC = "W20";
NET "adc_spi_cs_dac1_n_o[1]" LOC = "W19";
NET "adc_spi_cs_dac2_n_o[1]" LOC = "Y19";
NET "adc_spi_cs_dac3_n_o[1]" LOC = "AA19";
NET "adc_spi_cs_dac4_n_o[1]" LOC = "AB19";
NET "adc_gpio_dac_clr_n_o[1]" LOC = "Y20";
NET "adc_gpio_led_acq_o[1]" LOC = "AC22";
NET "adc_gpio_led_trig_o[1]" LOC = "AA22";
NET "adc_gpio_ssr_ch1_o[7]" LOC = "AC19";
NET "adc_gpio_ssr_ch1_o[8]" LOC = "AD19";
NET "adc_gpio_ssr_ch1_o[9]" LOC = "AC20";
NET "adc_gpio_ssr_ch1_o[10]" LOC = "AD17";
NET "adc_gpio_ssr_ch1_o[11]" LOC = "AB21";
NET "adc_gpio_ssr_ch1_o[12]" LOC = "AC21";
NET "adc_gpio_ssr_ch1_o[13]" LOC = "AC24";
NET "adc_gpio_ssr_ch2_o[7]" LOC = "AE19";
NET "adc_gpio_ssr_ch2_o[8]" LOC = "AF23";
NET "adc_gpio_ssr_ch2_o[9]" LOC = "AE24";
NET "adc_gpio_ssr_ch2_o[10]" LOC = "AF24";
NET "adc_gpio_ssr_ch2_o[11]" LOC = "AD22";
NET "adc_gpio_ssr_ch2_o[12]" LOC = "AB20";
NET "adc_gpio_ssr_ch2_o[13]" LOC = "AE22";
NET "adc_gpio_ssr_ch3_o[7]" LOC = "AB12";
NET "adc_gpio_ssr_ch3_o[8]" LOC = "AC12";
NET "adc_gpio_ssr_ch3_o[9]" LOC = "AE15";
NET "adc_gpio_ssr_ch3_o[10]" LOC = "AF15";
NET "adc_gpio_ssr_ch3_o[11]" LOC = "Y16";
NET "adc_gpio_ssr_ch3_o[12]" LOC = "AB16";
NET "adc_gpio_ssr_ch3_o[13]" LOC = "AF19";
NET "adc_gpio_ssr_ch4_o[7]" LOC = "AC11";
NET "adc_gpio_ssr_ch4_o[8]" LOC = "AD11";
NET "adc_gpio_ssr_ch4_o[9]" LOC = "AE13";
NET "adc_gpio_ssr_ch4_o[10]" LOC = "AF13";
NET "adc_gpio_ssr_ch4_o[11]" LOC = "AJ15";
NET "adc_gpio_ssr_ch4_o[12]" LOC = "AD10";
NET "adc_gpio_ssr_ch4_o[13]" LOC = "AK15";
NET "adc_gpio_si570_oe_o[1]" LOC = "AE10";
NET "adc_si570_scl_b[1]" LOC = "AF21";
NET "adc_si570_sda_b[1]" LOC = "AE21";
NET "adc_one_wire_b[1]" LOC = "AD24";
# IO standards
NET "adc_ext_trigger_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_dco_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_fr_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_out?_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_spi_din_i[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_dout_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_sck_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_cs_adc_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_cs_dac?_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_dac_clr_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_led_acq_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_led_trig_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_ssr_ch?_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_si570_oe_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_si570_scl_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_si570_sda_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_one_wire_b[*]" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "gen_fmc_mezzanine[?].*/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 2.0 ns;
INST "gen_fmc_mezzanine[0].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X66Y189;
INST "gen_fmc_mezzanine[1].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X69Y2;
#----------------------------------------
# IOB exceptions
#----------------------------------------
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_i2c/U_Wrapped_I2C/*" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_onewire/*" IOB = FALSE;
#----------------------------------------
# Clocks
#----------------------------------------
NET "adc_dco_p_i[0]" TNM_NET = adc0_dco;
NET "adc_dco_n_i[0]" TNM_NET = adc0_dco;
TIMESPEC TS_adc0_dco = PERIOD "adc0_dco" 2.5 ns HIGH 50%;
NET "adc_dco_p_i[1]" TNM_NET = adc1_dco;
NET "adc_dco_n_i[1]" TNM_NET = adc1_dco;
TIMESPEC TS_adc1_dco = PERIOD "adc1_dco" 2.5 ns HIGH 50%;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "gen_fmc_mezzanine[0].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk;
NET "gen_fmc_mezzanine[1].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs1_clk;
TIMEGRP "adc0_sync_ffs" = "sync_ffs" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_ffs" = "sync_ffs" EXCEPT "fs1_clk";
#TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
#TIMESPEC TS_adc1_sync_ffs = FROM fs1_clk TO "adc1_sync_ffs" TIG;
TIMEGRP "adc0_sync_reg" = "sync_reg" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_reg" = "sync_reg" EXCEPT "fs1_clk";
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_adc1_sync_reg = FROM fs1_clk TO "adc1_sync_reg" 8ns DATAPATHONLY;
# No sync words used in FMC-ADC
#TIMESPEC TS_adc0_sync_word = FROM sync_word TO fs0_clk 30ns DATAPATHONLY;
#TIMESPEC TS_adc1_sync_word = FROM sync_word TO fs1_clk 30ns DATAPATHONLY;
hdl/syn/wrtd_ref_svec_fd_x2/Manifest.py 0 → 100644
View file @ 0f59185c
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "wrtd_ref_svec_fd_x2"
syn_project = "wrtd_ref_svec_fd_x2.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
files = [
"wrtd_ref_svec_fd_x2.ucf",
"buildinfo_pkg.vhd",
fetchto + "/fmc-delay-1ns-8cha/hdl/syn/svec/svec-fd0.ucf",
fetchto + "/fmc-delay-1ns-8cha/hdl/syn/svec/svec-fd1.ucf",
]
modules = {
"local" : [
"../../top/wrtd_ref_svec_fd_x2",
],
}
#syn_pre_project_cmd = "make -C ../../../software/firmware"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/syn/wrtd_ref_svec_fd_x2/syn_extra_steps.tcl 0 → 100644
View file @ 0f59185c
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/syn/wrtd_ref_svec_fd_x2/wrtd_ref_svec_fd_x2.ucf 0 → 100644
View file @ 0f59185c
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
NET "fp_gpio3_b" TNM_NET = fp_gpio3;
TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50%;
NET "fmc0_fd_clk_ref_n_i" TNM_NET = fmc0_fd_clk_ref_n_i;
TIMESPEC TS_fmc0_fd_clk_ref_n_i = PERIOD "fmc0_fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# IMPORTANT: timing constraints are also coming from SVEC base UCF files
# Declaration of domains
NET "dcm0_clk_ref_0" TNM_NET = fd0_clk;
NET "dcm1_clk_ref_0" TNM_NET = fd1_clk;
# Exceptions for crossings via gc_sync_ffs
#TIMEGRP "fdl_sync_ffs" = "sync_ffs" EXCEPT "fdl_clk";
#TIMEGRP "tdc_sync_ffs" = "sync_ffs" EXCEPT "tdc_clk";
#TIMESPEC TS_fdl_sync_ffs = FROM fdl_clk TO "fdl_sync_ffs" TIG;
#TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk TO "tdc_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
#TIMEGRP "fdl_sync_reg" = "sync_reg" EXCEPT "fdl_clk";
#TIMEGRP "tdc_sync_reg" = "sync_reg" EXCEPT "tdc_clk";
#TIMESPEC TS_fdl_sync_reg = FROM fdl_clk TO "fdl_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_tdc_sync_reg = FROM tdc_clk TO "tdc_sync_reg" 8ns DATAPATHONLY;
hdl/syn/wrtd_ref_svec_tdc_x2/Manifest.py 0 → 100644
View file @ 0f59185c
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "wrtd_ref_svec_tdc_x2"
syn_project = "wrtd_ref_svec_tdc_x2.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
files = [
"buildinfo_pkg.vhd",
fetchto + "/fmc-tdc/hdl/syn/svec/svec-tdc0.ucf",
fetchto + "/fmc-tdc/hdl/syn/svec/svec-tdc1.ucf",
"wrtd_ref_svec_tdc_x2.ucf",
]
modules = {
"local" : [
"../../top/wrtd_ref_svec_tdc_x2",
],
}
syn_pre_project_cmd = "make -C ../../../software/firmware"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/syn/wrtd_ref_svec_tdc_x2/syn_extra_steps.tcl 0 → 100644
View file @ 0f59185c
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/syn/wrtd_ref_svec_tdc_x2/wrtd_ref_svec_tdc_x2.ucf 0 → 100644
View file @ 0f59185c
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
NET "fp_gpio3_b" TNM_NET = fp_gpio3;
TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50%;
NET "fmc0_tdc_clk_125m_n_i" TNM_NET = fmc0_tdc_clk_125m_n_i;
TIMESPEC TS_fmc0_tdc_clk_125m_n_i = PERIOD "fmc0_tdc_clk_125m_n_i" 8 ns HIGH 50%;
NET "fmc1_tdc_clk_125m_n_i" TNM_NET = fmc1_tdc_clk_125m_n_i;
TIMESPEC TS_fmc1_tdc_clk_125m_n_i = PERIOD "fmc1_tdc_clk_125m_n_i" 8 ns HIGH 50%;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# IMPORTANT: timing constraints are also coming from SVEC base UCF files
# Declaration of domains
NET "tdc0_clk_125m" TNM_NET = tdc0_clk;
NET "tdc1_clk_125m" TNM_NET = tdc1_clk;
# Exceptions for crossings via gc_sync_ffs
TIMEGRP "tdc0_sync_ffs" = "sync_ffs" EXCEPT "tdc0_clk";
#TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk TO "tdc_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
#TIMEGRP "tdc_sync_reg" = "sync_reg" EXCEPT "tdc_clk";
#TIMESPEC TS_tdc_sync_reg = FROM tdc_clk TO "tdc_sync_reg" 8ns DATAPATHONLY;
hdl/testbench/wrtd_ref_spec150t_adc/Manifest.py
View file @ 0f59185c
......@@ -18,7 +18,7 @@ include_dirs = [
fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
fetchto + "/general-cores/sim",
fetchto + "/mock-turtle/hdl/testbench/include",
fetchto + "/fmc-adc-100m14b4cha-gw/hdl/testbench/include",
fetchto + "/fmc-adc-100m14b4cha/hdl/testbench/include",
]
files = [
......
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
View file @ 0f59185c
......@@ -241,7 +241,7 @@ module dut_env
always@(negedge clk_400m_adc)
begin
#625ps;
if(adc_div == 1) begin
if(adc_div == 3) begin
adc0_fr <= ~adc0_fr;
adc_div <= 0;
end
......
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
View file @ 0f59185c
......@@ -27,12 +27,21 @@
`include "gn4124_bfm.svh"
`include "wrtd_driver.svh"
`include "fmc_adc_mezzanine_mmap.v"
`include "fmc_adc_100Ms_csr.v"
`include "fmc_adc_100Ms_channel_regs.v"
`include "fmc_adc_eic_regs.v"
`define DMA_BASE 'h00c0
`define VIC_BASE 'h0100
`define ADC_CSR_BASE 'h5000
`define ADC_EIC_BASE 'h5500
`define ADC_OFFSET 'h4000
`define ADC_CSR_BASE `ADC_OFFSET + `ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR
`define ADC_EIC_BASE `ADC_OFFSET + `ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC
`define ADC_CH1_BASE `ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH1
`define ADC_CH2_BASE `ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH2
`define ADC_CH3_BASE `ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH3
`define ADC_CH4_BASE `ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH4
module main;
......@@ -69,6 +78,7 @@ module main;
begin
accA = hostA.get_accessor();
accA.set_default_xfer_size(4);
devA = new (accA, MT_BASE, MtIrqMonitorA, "DUT:A");
devA.init();
devA.add_rule ( "rule0" );
......@@ -83,17 +93,17 @@ module main;
accA.write(`VIC_BASE + 'h0, 'h1);
// Config DUTA to trigger on external trigger and get 64 samples
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h40);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h01);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_CALIB, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_CALIB, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_CALIB, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_CALIB, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h7fff);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h7fff);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h7fff);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h7fff);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h0000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h0040);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0001);
accA.write(`ADC_CH1_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accA.write(`ADC_CH2_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accA.write(`ADC_CH3_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accA.write(`ADC_CH4_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accA.write(`ADC_CH1_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
accA.write(`ADC_CH2_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
accA.write(`ADC_CH3_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
accA.write(`ADC_CH4_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
......@@ -123,17 +133,17 @@ module main;
accB.write(`VIC_BASE + 'h0, 'h1);
// Config DUTB to trigger on WRTD and get 64 samples
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h40);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h01);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_CALIB, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_CALIB, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_CALIB, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_CALIB, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h7fff);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h7fff);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h7fff);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h7fff);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h0000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h0040);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0001);
accB.write(`ADC_CH1_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accB.write(`ADC_CH2_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accB.write(`ADC_CH3_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accB.write(`ADC_CH4_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accB.write(`ADC_CH1_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
accB.write(`ADC_CH2_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
accB.write(`ADC_CH3_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
accB.write(`ADC_CH4_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
expected = 'h39;
accB.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
......
hdl/top/wrtd_ref_spec150t_adc/Manifest.py
View file @ 0f59185c
......@@ -13,6 +13,6 @@ modules = {
"https://ohwr.org/project/ddr3-sp6-core.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/spec.git",
"https://ohwr.org/project/fmc-adc-100m14b4cha-gw.git",
"https://ohwr.org/project/fmc-adc-100m14b4cha.git",
],
}
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
View file @ 0f59185c
......@@ -290,10 +290,6 @@ architecture arch of wrtd_ref_spec150t_adc is
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
-- GN4124 core DMA port to DDR wishbone bus
signal gn_wb_ddr_in : t_wishbone_master_in;
signal gn_wb_ddr_out : t_wishbone_master_out;
-- MT endpoints
signal rmq_endpoint_out : t_mt_rmq_endpoint_iface_out;
signal rmq_endpoint_in : t_mt_rmq_endpoint_iface_in;
......@@ -677,9 +673,6 @@ begin -- architecture arch
mezz_one_wire_b => fmc0_adc_one_wire_b,
sys_scl_b => fmc0_scl_b,
sys_sda_b => fmc0_sda_b,
wr_tm_link_up_i => tm_link_up,
wr_tm_time_valid_i => tm_time_valid_sync,
wr_tm_tai_i => tm_tai,
......
hdl/top/wrtd_ref_svec_adc_x2/Manifest.py 0 → 100644
View file @ 0f59185c
files = [
"wrtd_ref_svec_adc_x2.vhd",
"wrtd_adc_x2_host_map.vhd",
"wrtd_adc_x2_fmc_map.vhd",
]
fetchto = "../../../dependencies"
modules = {
"git" : [
"https://ohwr.org/project/svec.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/urv-core.git",
"https://ohwr.org/project/mock-turtle.git",
"https://ohwr.org/project/fmc-adc-100m14b4cha.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
hdl/top/wrtd_ref_svec_adc_x2/wrtd_adc_x2_fmc_map.cheby 0 → 100644
View file @ 0f59185c
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: wrtd_adc_x2_fmc_map
bus: wb-32-be
description: WRTD ADC x2 dedicated peripheral map
size: 0x4000
x-hdl:
busgroup: True
pipeline: wr,rd
children:
- submap:
name: adc0_trigin
address: 0x0000
size: 0x1000
description: FMC ADC0 trigin
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: adc0_trigout
address: 0x1000
size: 0x1000
description: FMC ADC0 trigout
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: adc1_trigin
address: 0x2000
size: 0x1000
description: FMC ADC1 trigin
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: adc1_trigout
address: 0x3000
size: 0x1000
description: FMC ADC1 trigout
interface: wb-32-be
x-hdl:
busgroup: True
hdl/top/wrtd_ref_svec_adc_x2/wrtd_adc_x2_fmc_map.vhd 0 → 100644
View file @ 0f59185c
This diff is collapsed.
hdl/top/wrtd_ref_svec_adc_x2/wrtd_adc_x2_host_map.cheby 0 → 100644
View file @ 0f59185c
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: wrtd_adc_x2_host_map
bus: wb-32-be
description: WRTD FMC-ADC-100M memory map
size: 0x40000
x-hdl:
busgroup: True
pipeline: wr,rd
children:
- submap:
name: metadata
address: 0x4000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
description: a ROM containing the application metadata
- submap:
name: adc0
address: 0x6000
size: 0x2000
description: FMC ADC Mezzanine slot 1
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: adc1
address: 0x8000
size: 0x2000
description: FMC ADC Mezzanine slot 2
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: mt
address: 0x20000
size: 0x20000
description: Mock-turtle
interface: wb-32-be
x-hdl:
busgroup: True
hdl/top/wrtd_ref_svec_adc_x2/wrtd_adc_x2_host_map.vhd 0 → 100644
View file @ 0f59185c
-- Do not edit. Generated on Thu Feb 25 09:14:33 2021 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- --gen-hdl=wrtd_adc_x2_host_map.vhd -i wrtd_adc_x2_host_map.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity wrtd_adc_x2_host_map is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- a ROM containing the application metadata
metadata_i : in t_wishbone_master_in;
metadata_o : out t_wishbone_master_out;
-- FMC ADC Mezzanine slot 1
adc0_i : in t_wishbone_master_in;
adc0_o : out t_wishbone_master_out;
-- FMC ADC Mezzanine slot 2
adc1_i : in t_wishbone_master_in;
adc1_o : out t_wishbone_master_out;
-- Mock-turtle
mt_i : in t_wishbone_master_in;
mt_o : out t_wishbone_master_out
);
end wrtd_adc_x2_host_map;
architecture syn of wrtd_adc_x2_host_map is
signal adr_int : std_logic_vector(17 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_re : std_logic;
signal metadata_we : std_logic;
signal metadata_wt : std_logic;
signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal adc0_re : std_logic;
signal adc0_we : std_logic;
signal adc0_wt : std_logic;
signal adc0_rt : std_logic;
signal adc0_tr : std_logic;
signal adc0_wack : std_logic;
signal adc0_rack : std_logic;
signal adc1_re : std_logic;
signal adc1_we : std_logic;
signal adc1_wt : std_logic;
signal adc1_rt : std_logic;
signal adc1_tr : std_logic;
signal adc1_wack : std_logic;
signal adc1_rack : std_logic;
signal mt_re : std_logic;
signal mt_we : std_logic;
signal mt_wt : std_logic;
signal mt_rt : std_logic;
signal mt_tr : std_logic;
signal mt_wack : std_logic;
signal mt_rack : std_logic;
signal rd_req_d0 : std_logic;
signal rd_adr_d0 : std_logic_vector(17 downto 2);
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
signal wr_ack_d0 : std_logic;
begin
-- WB decode signals
adr_int <= wb_i.adr(17 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- pipelining for rd-in+rd-out+wr-in+wr-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_req_d0 <= '0';
rd_ack_int <= '0';
wr_req_d0 <= '0';
wr_ack_int <= '0';
else
rd_req_d0 <= rd_req_int;
rd_adr_d0 <= adr_int;
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
wr_ack_int <= wr_ack_d0;
end if;
end if;
end process;
-- Interface metadata
metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
metadata_wt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
metadata_wt <= (metadata_wt or metadata_we) and not metadata_wack;
end if;
end if;
end process;
metadata_o.cyc <= metadata_tr;
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & rd_adr_d0(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= wr_sel_d0;
metadata_o.we <= metadata_wt;
metadata_o.dat <= wr_dat_d0;
-- Interface adc0
adc0_tr <= adc0_wt or adc0_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
adc0_rt <= '0';
adc0_wt <= '0';
else
adc0_rt <= (adc0_rt or adc0_re) and not adc0_rack;
adc0_wt <= (adc0_wt or adc0_we) and not adc0_wack;
end if;
end if;
end process;
adc0_o.cyc <= adc0_tr;
adc0_o.stb <= adc0_tr;
adc0_wack <= adc0_i.ack and adc0_wt;
adc0_rack <= adc0_i.ack and adc0_rt;
adc0_o.adr <= ((18 downto 0 => '0') & rd_adr_d0(12 downto 2)) & (1 downto 0 => '0');
adc0_o.sel <= wr_sel_d0;
adc0_o.we <= adc0_wt;
adc0_o.dat <= wr_dat_d0;
-- Interface adc1
adc1_tr <= adc1_wt or adc1_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
adc1_rt <= '0';
adc1_wt <= '0';
else
adc1_rt <= (adc1_rt or adc1_re) and not adc1_rack;
adc1_wt <= (adc1_wt or adc1_we) and not adc1_wack;
end if;
end if;
end process;
adc1_o.cyc <= adc1_tr;
adc1_o.stb <= adc1_tr;
adc1_wack <= adc1_i.ack and adc1_wt;
adc1_rack <= adc1_i.ack and adc1_rt;
adc1_o.adr <= ((18 downto 0 => '0') & rd_adr_d0(12 downto 2)) & (1 downto 0 => '0');
adc1_o.sel <= wr_sel_d0;
adc1_o.we <= adc1_wt;
adc1_o.dat <= wr_dat_d0;
-- Interface mt
mt_tr <= mt_wt or mt_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
mt_rt <= '0';
mt_wt <= '0';
else
mt_rt <= (mt_rt or mt_re) and not mt_rack;
mt_wt <= (mt_wt or mt_we) and not mt_wack;
end if;
end if;
end process;
mt_o.cyc <= mt_tr;
mt_o.stb <= mt_tr;
mt_wack <= mt_i.ack and mt_wt;
mt_rack <= mt_i.ack and mt_rt;
mt_o.adr <= ((14 downto 0 => '0') & rd_adr_d0(16 downto 2)) & (1 downto 0 => '0');
mt_o.sel <= wr_sel_d0;
mt_o.we <= mt_wt;
mt_o.dat <= wr_dat_d0;
-- Process for write requests.
process (rd_adr_d0, wr_req_d0, metadata_wack, adc0_wack, adc1_wack, mt_wack) begin
metadata_we <= '0';
adc0_we <= '0';
adc1_we <= '0';
mt_we <= '0';
case rd_adr_d0(17 downto 17) is
when "0" =>
case rd_adr_d0(16 downto 13) is
when "0010" =>
-- Submap metadata
metadata_we <= wr_req_d0;
wr_ack_d0 <= metadata_wack;
when "0011" =>
-- Submap adc0
adc0_we <= wr_req_d0;
wr_ack_d0 <= adc0_wack;
when "0100" =>
-- Submap adc1
adc1_we <= wr_req_d0;
wr_ack_d0 <= adc1_wack;
when others =>
wr_ack_d0 <= wr_req_d0;
end case;
when "1" =>
-- Submap mt
mt_we <= wr_req_d0;
wr_ack_d0 <= mt_wack;
when others =>
wr_ack_d0 <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (rd_adr_d0, rd_req_d0, metadata_i.dat, metadata_rack, adc0_i.dat, adc0_rack, adc1_i.dat, adc1_rack, mt_i.dat, mt_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
metadata_re <= '0';
adc0_re <= '0';
adc1_re <= '0';
mt_re <= '0';
case rd_adr_d0(17 downto 17) is
when "0" =>
case rd_adr_d0(16 downto 13) is
when "0010" =>
-- Submap metadata
metadata_re <= rd_req_d0;
rd_dat_d0 <= metadata_i.dat;
rd_ack_d0 <= metadata_rack;
when "0011" =>
-- Submap adc0
adc0_re <= rd_req_d0;
rd_dat_d0 <= adc0_i.dat;
rd_ack_d0 <= adc0_rack;
when "0100" =>
-- Submap adc1
adc1_re <= rd_req_d0;
rd_dat_d0 <= adc1_i.dat;
rd_ack_d0 <= adc1_rack;
when others =>
rd_ack_d0 <= rd_req_d0;
end case;
when "1" =>
-- Submap mt
mt_re <= rd_req_d0;
rd_dat_d0 <= mt_i.dat;
rd_ack_d0 <= mt_rack;
when others =>
rd_ack_d0 <= rd_req_d0;
end case;
end process;
end syn;
hdl/top/wrtd_ref_svec_adc_x2/wrtd_ref_svec_adc_x2.vhd 0 → 100644
View file @ 0f59185c
This diff is collapsed.
hdl/top/wrtd_ref_svec_fd_x2/Manifest.py 0 → 100644
View file @ 0f59185c
files = [
"wrtd_ref_svec_fd_x2.vhd",
"wrtd_fd_x2_host_map.vhd",
]
fetchto = "../../../dependencies"
modules = {
"git" : [
"https://ohwr.org/project/svec.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/urv-core.git",
"https://ohwr.org/project/mock-turtle.git",
"https://ohwr.org/project/fmc-delay-1ns-8cha.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
hdl/top/wrtd_ref_svec_fd_x2/wrtd_fd_x2_host_map.cheby 0 → 100644
View file @ 0f59185c
memory-map:
name: wrtd_fd_x2_host_map
bus: wb-32-be
size: 0x80000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
address: 0x4000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: fd
description: FD
address: 0x10000
size: 0x10000
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: mt
description: Mock Turtle
address: 0x20000
size: 0x20000
interface: wb-32-be
x-hdl:
busgroup: True
hdl/top/wrtd_ref_svec_fd_x2/wrtd_fd_x2_host_map.vhd 0 → 100644
View file @ 0f59185c
-- Do not edit. Generated on Tue Feb 23 14:50:12 2021 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- --gen-hdl -i wrtd_fd_x2_host_map.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity wrtd_fd_x2_host_map is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- a ROM containing the carrier metadata
metadata_i : in t_wishbone_master_in;
metadata_o : out t_wishbone_master_out;
-- FD
fd_i : in t_wishbone_master_in;
fd_o : out t_wishbone_master_out;
-- Mock Turtle
mt_i : in t_wishbone_master_in;
mt_o : out t_wishbone_master_out
);
end wrtd_fd_x2_host_map;
architecture syn of wrtd_fd_x2_host_map is
signal adr_int : std_logic_vector(18 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_re : std_logic;
signal metadata_we : std_logic;
signal metadata_wt : std_logic;
signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal fd_re : std_logic;
signal fd_we : std_logic;
signal fd_wt : std_logic;
signal fd_rt : std_logic;
signal fd_tr : std_logic;
signal fd_wack : std_logic;
signal fd_rack : std_logic;
signal mt_re : std_logic;
signal mt_we : std_logic;
signal mt_wt : std_logic;
signal mt_rt : std_logic;
signal mt_tr : std_logic;
signal mt_wack : std_logic;
signal mt_rack : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(18 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- WB decode signals
adr_int <= wb_i.adr(18 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= adr_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
end if;
end if;
end process;
-- Interface metadata
metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
metadata_wt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
metadata_wt <= (metadata_wt or metadata_we) and not metadata_wack;
end if;
end if;
end process;
metadata_o.cyc <= metadata_tr;
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & adr_int(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= wr_sel_d0;
metadata_o.we <= metadata_wt;
metadata_o.dat <= wr_dat_d0;
-- Interface fd
fd_tr <= fd_wt or fd_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fd_rt <= '0';
fd_wt <= '0';
else
fd_rt <= (fd_rt or fd_re) and not fd_rack;
fd_wt <= (fd_wt or fd_we) and not fd_wack;
end if;
end if;
end process;
fd_o.cyc <= fd_tr;
fd_o.stb <= fd_tr;
fd_wack <= fd_i.ack and fd_wt;
fd_rack <= fd_i.ack and fd_rt;
fd_o.adr <= ((15 downto 0 => '0') & adr_int(15 downto 2)) & (1 downto 0 => '0');
fd_o.sel <= wr_sel_d0;
fd_o.we <= fd_wt;
fd_o.dat <= wr_dat_d0;
-- Interface mt
mt_tr <= mt_wt or mt_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
mt_rt <= '0';
mt_wt <= '0';
else
mt_rt <= (mt_rt or mt_re) and not mt_rack;
mt_wt <= (mt_wt or mt_we) and not mt_wack;
end if;
end if;
end process;
mt_o.cyc <= mt_tr;
mt_o.stb <= mt_tr;
mt_wack <= mt_i.ack and mt_wt;
mt_rack <= mt_i.ack and mt_rt;
mt_o.adr <= ((14 downto 0 => '0') & adr_int(16 downto 2)) & (1 downto 0 => '0');
mt_o.sel <= wr_sel_d0;
mt_o.we <= mt_wt;
mt_o.dat <= wr_dat_d0;
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, metadata_wack, fd_wack, mt_wack) begin
metadata_we <= '0';
fd_we <= '0';
mt_we <= '0';
case wr_adr_d0(18 downto 17) is
when "00" =>
case wr_adr_d0(16 downto 16) is
when "0" =>
-- Submap metadata
metadata_we <= wr_req_d0;
wr_ack_int <= metadata_wack;
when "1" =>
-- Submap fd
fd_we <= wr_req_d0;
wr_ack_int <= fd_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "01" =>
-- Submap mt
mt_we <= wr_req_d0;
wr_ack_int <= mt_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (adr_int, rd_req_int, metadata_i.dat, metadata_rack, fd_i.dat, fd_rack, mt_i.dat, mt_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
metadata_re <= '0';
fd_re <= '0';
mt_re <= '0';
case adr_int(18 downto 17) is
when "00" =>
case adr_int(16 downto 16) is
when "0" =>
-- Submap metadata
metadata_re <= rd_req_int;
rd_dat_d0 <= metadata_i.dat;
rd_ack_d0 <= metadata_rack;
when "1" =>
-- Submap fd
fd_re <= rd_req_int;
rd_dat_d0 <= fd_i.dat;
rd_ack_d0 <= fd_rack;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "01" =>
-- Submap mt
mt_re <= rd_req_int;
rd_dat_d0 <= mt_i.dat;
rd_ack_d0 <= mt_rack;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
hdl/top/wrtd_ref_svec_fd_x2/wrtd_ref_svec_fd_x2.vhd 0 → 100644
View file @ 0f59185c
This diff is collapsed.
hdl/top/wrtd_ref_svec_tdc_fd/Manifest.py
View file @ 0f59185c
......@@ -12,7 +12,7 @@ modules = {
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/urv-core.git",
"https://ohwr.org/project/mock-turtle.git",
"https://ohwr.org/project/fmc-tdc-1ns-5cha-gw.git",
"https://ohwr.org/project/fmc-tdc.git",
"https://ohwr.org/project/fmc-delay-1ns-8cha.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
......
hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd
View file @ 0f59185c
......@@ -312,7 +312,7 @@ architecture arch of wrtd_ref_svec_tdc_fd is
constant c_WB_SLAVE_MT : integer := 3;
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
constant c_METADATA_ADDR : t_wishbone_address := x"0000_4000";
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT_ADDR :
......@@ -392,29 +392,8 @@ architecture arch of wrtd_ref_svec_tdc_fd is
attribute keep of tdc_clk_125m : signal is "TRUE";
attribute keep of dcm1_clk_ref_0 : signal is "TRUE";
-- I2C EEPROM
signal eeprom_sda_in : std_logic;
signal eeprom_sda_out : std_logic;
signal eeprom_scl_in : std_logic;
signal eeprom_scl_out : std_logic;
-- VME
signal vme_data_b_out : std_logic_vector(31 downto 0);
signal vme_addr_b_out : std_logic_vector(31 downto 1);
signal vme_lword_n_b_out : std_logic;
signal vme_data_dir_int : std_logic;
signal vme_addr_dir_int : std_logic;
signal vme_ga : std_logic_vector(5 downto 0);
signal vme_berr_n : std_logic;
signal vme_irq_n : std_logic_vector(7 downto 1);
signal vme_access_led : std_logic;
-- SFP
signal sfp_sda_in : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
-- LEDs and GPIO
signal pps : std_logic;
signal pps_led : std_logic;
......@@ -488,7 +467,7 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => c_WRTD_NODE_ID,
g_VERSION => x"0100_0000",
g_VERSION => x"0100_0001",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map (
......@@ -722,6 +701,8 @@ begin -- architecture arch
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => rst_sys_62m5_n,
fmc_id_i => '0',
fmc_present_n_i => fmc0_prsnt_m2c_n_i,
pll_sclk_o => fmc0_tdc_pll_sclk_o,
pll_sdi_o => fmc0_tdc_pll_sdi_o,
pll_cs_o => fmc0_tdc_pll_cs_n_o,
......@@ -751,17 +732,18 @@ begin -- architecture arch
term_en_3_o => fmc0_tdc_term_en_3_o,
term_en_4_o => fmc0_tdc_term_en_4_o,
term_en_5_o => fmc0_tdc_term_en_5_o,
tdc_led_status_o => fmc0_tdc_led_status_o,
tdc_led_trig1_o => fmc0_tdc_led_trig1_o,
tdc_led_trig2_o => fmc0_tdc_led_trig2_o,
tdc_led_trig3_o => fmc0_tdc_led_trig3_o,
tdc_led_trig4_o => fmc0_tdc_led_trig4_o,
tdc_led_trig5_o => fmc0_tdc_led_trig5_o,
tdc_led_stat_o => fmc0_tdc_led_status_o,
tdc_led_trig_o(0) => fmc0_tdc_led_trig1_o,
tdc_led_trig_o(1) => fmc0_tdc_led_trig2_o,
tdc_led_trig_o(2) => fmc0_tdc_led_trig3_o,
tdc_led_trig_o(3) => fmc0_tdc_led_trig4_o,
tdc_led_trig_o(4) => fmc0_tdc_led_trig5_o,
mezz_scl_i => '0',
mezz_sda_i => '0',
mezz_scl_o => open,
mezz_sda_o => open,
mezz_one_wire_b => fmc0_tdc_one_wire_b,
fmc_present_n_i => '0',
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
......@@ -860,7 +842,7 @@ begin -- architecture arch
i2c_scl_i => '0',
i2c_sda_oen_o => open,
i2c_sda_i => '0',
fmc_present_n_i => '0',
fmc_present_n_i => fmc1_prsnt_m2c_n_i,
wb_adr_i => fmc1_mux_wb_out.adr,
wb_dat_i => fmc1_mux_wb_out.dat,
wb_dat_o => fmc1_mux_wb_in.dat,
......
hdl/top/wrtd_ref_svec_tdc_x2/Manifest.py 0 → 100644
View file @ 0f59185c
files = [
"wrtd_ref_svec_tdc_x2.vhd",
"wrtd_tdc_x2_host_map.vhd",
"wrtd_tdc_x2_fmc_map.vhd",
]
fetchto = "../../../dependencies"
modules = {
"git" : [
"https://ohwr.org/project/svec.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/urv-core.git",
"https://ohwr.org/project/mock-turtle.git",
"https://ohwr.org/project/fmc-tdc.git",
"https://ohwr.org/project/fmc-delay-1ns-8cha.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
hdl/top/wrtd_ref_svec_tdc_x2/wrtd_ref_svec_tdc_x2.vhd 0 → 100644
View file @ 0f59185c
This diff is collapsed.
hdl/top/wrtd_ref_svec_tdc_x2/wrtd_tdc_x2_fmc_map.cheby 0 → 100644
View file @ 0f59185c
memory-map:
name: wrtd_tdc_x2_fmc_map
bus: wb-32-be
size: 0x20000
x-hdl:
busgroup: True
children:
- submap:
name: tdc0
description: TDC0
address: 0x00000
size: 0x10000
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: tdc1
description: TDC1
address: 0x10000
size: 0x10000
interface: wb-32-be
x-hdl:
busgroup: True
hdl/top/wrtd_ref_svec_tdc_x2/wrtd_tdc_x2_fmc_map.vhd 0 → 100644
View file @ 0f59185c
-- Do not edit. Generated on Tue Feb 16 14:11:11 2021 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- --gen-hdl wrtd_tdc_x2_fmc_map.vhd -i wrtd_tdc_x2_fmc_map.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity wrtd_tdc_x2_fmc_map is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- TDC0
tdc0_i : in t_wishbone_master_in;
tdc0_o : out t_wishbone_master_out;
-- TDC1
tdc1_i : in t_wishbone_master_in;
tdc1_o : out t_wishbone_master_out
);
end wrtd_tdc_x2_fmc_map;
architecture syn of wrtd_tdc_x2_fmc_map is
signal adr_int : std_logic_vector(16 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal tdc0_re : std_logic;
signal tdc0_we : std_logic;
signal tdc0_wt : std_logic;
signal tdc0_rt : std_logic;
signal tdc0_tr : std_logic;
signal tdc0_wack : std_logic;
signal tdc0_rack : std_logic;
signal tdc1_re : std_logic;
signal tdc1_we : std_logic;
signal tdc1_wt : std_logic;
signal tdc1_rt : std_logic;
signal tdc1_tr : std_logic;
signal tdc1_wack : std_logic;
signal tdc1_rack : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(16 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- WB decode signals
adr_int <= wb_i.adr(16 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= adr_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
end if;
end if;
end process;
-- Interface tdc0
tdc0_tr <= tdc0_wt or tdc0_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
tdc0_rt <= '0';
tdc0_wt <= '0';
else
tdc0_rt <= (tdc0_rt or tdc0_re) and not tdc0_rack;
tdc0_wt <= (tdc0_wt or tdc0_we) and not tdc0_wack;
end if;
end if;
end process;
tdc0_o.cyc <= tdc0_tr;
tdc0_o.stb <= tdc0_tr;
tdc0_wack <= tdc0_i.ack and tdc0_wt;
tdc0_rack <= tdc0_i.ack and tdc0_rt;
tdc0_o.adr <= ((15 downto 0 => '0') & adr_int(15 downto 2)) & (1 downto 0 => '0');
tdc0_o.sel <= wr_sel_d0;
tdc0_o.we <= tdc0_wt;
tdc0_o.dat <= wr_dat_d0;
-- Interface tdc1
tdc1_tr <= tdc1_wt or tdc1_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
tdc1_rt <= '0';
tdc1_wt <= '0';
else
tdc1_rt <= (tdc1_rt or tdc1_re) and not tdc1_rack;
tdc1_wt <= (tdc1_wt or tdc1_we) and not tdc1_wack;
end if;
end if;
end process;
tdc1_o.cyc <= tdc1_tr;
tdc1_o.stb <= tdc1_tr;
tdc1_wack <= tdc1_i.ack and tdc1_wt;
tdc1_rack <= tdc1_i.ack and tdc1_rt;
tdc1_o.adr <= ((15 downto 0 => '0') & adr_int(15 downto 2)) & (1 downto 0 => '0');
tdc1_o.sel <= wr_sel_d0;
tdc1_o.we <= tdc1_wt;
tdc1_o.dat <= wr_dat_d0;
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, tdc0_wack, tdc1_wack) begin
tdc0_we <= '0';
tdc1_we <= '0';
case wr_adr_d0(16 downto 16) is
when "0" =>
-- Submap tdc0
tdc0_we <= wr_req_d0;
wr_ack_int <= tdc0_wack;
when "1" =>
-- Submap tdc1
tdc1_we <= wr_req_d0;
wr_ack_int <= tdc1_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (adr_int, rd_req_int, tdc0_i.dat, tdc0_rack, tdc1_i.dat, tdc1_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
tdc0_re <= '0';
tdc1_re <= '0';
case adr_int(16 downto 16) is
when "0" =>
-- Submap tdc0
tdc0_re <= rd_req_int;
rd_dat_d0 <= tdc0_i.dat;
rd_ack_d0 <= tdc0_rack;
when "1" =>
-- Submap tdc1
tdc1_re <= rd_req_int;
rd_dat_d0 <= tdc1_i.dat;
rd_ack_d0 <= tdc1_rack;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
hdl/top/wrtd_ref_svec_tdc_x2/wrtd_tdc_x2_host_map.cheby 0 → 100644
View file @ 0f59185c
memory-map:
name: wrtd_tdc_x2_host_map
bus: wb-32-be
size: 0x80000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
address: 0x4000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: tdc0
description: TDC0
address: 0x10000
size: 0x10000
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: tdc1
description: TDC1
address: 0x20000
size: 0x10000
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: mt
description: Mock Turtle
address: 0x40000
size: 0x20000
interface: wb-32-be
x-hdl:
busgroup: True
hdl/top/wrtd_ref_svec_tdc_x2/wrtd_tdc_x2_host_map.vhd 0 → 100644
View file @ 0f59185c
This diff is collapsed.
pytest/.gitignore 0 → 100644
View file @ 0f59185c
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
# SPDX-License-Identifier: CC0-1.0
__pycache__/
pytest/pytest.ini 0 → 100644
View file @ 0f59185c
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
# SPDX-License-Identifier: CC0-1.0
[pytest]
addopts = -v
testpaths =
tests
filterwarnings =
ignore::pytest.PytestCacheWarning
pytest/tests/WrtdTestHelper.py 0 → 100644
View file @ 0f59185c
This diff is collapsed.
pytest/tests/conftest.py 0 → 100644
View file @ 0f59185c
This diff is collapsed.
pytest/tests/test_WrtdRefDesigns.py 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/Makefile
View file @ 0f59185c
This diff is collapsed.
software/drivers/Kbuild
View file @ 0f59185c
......@@ -7,12 +7,22 @@ endif
endif
# add versions of used submodules
KBUILD_EXTRA_SYMBOLS += $(FMC_EXTRA_SYMBOLS-y)
ccflags-y += -DADDITIONAL_VERSIONS="$(SUBMODULE_VERSIONS)"
ccflags-y += -DDRV_VERSION=\"$(DRV_VERSION)\"
ccflags-y += -Wall -Werror
ccflags-y += -I$(FMC_ABS)/include
ccflags-y += -I$(ADC_ABS)/software/kernel
obj-m := wrtd-ref-spec150t-adc.o
obj-m += wrtd-ref-svec-tdc-fd.o
obj-m += wrtd-ref-svec-tdc-x2.o
obj-m += wrtd-ref-svec-fd-x2.o
obj-m += wrtd-ref-svec-adc-x2.o
wrtd-ref-spec150t-adc-objs := wrtd-ref-spec150t-adc-core.o
wrtd-ref-svec-tdc-fd-objs := wrtd-ref-svec-tdc-fd-core.o
wrtd-ref-svec-tdc-x2-objs := wrtd-ref-svec-tdc-x2-core.o
wrtd-ref-svec-fd-x2-objs := wrtd-ref-svec-fd-x2-core.o
wrtd-ref-svec-adc-x2-objs := wrtd-ref-svec-adc-x2-core.o
software/drivers/Makefile
View file @ 0f59185c
This diff is collapsed.
software/drivers/wrtd-ref-svec-adc-x2-core.c 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/drivers/wrtd-ref-svec-fd-x2-core.c 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/drivers/wrtd-ref-svec-tdc-x2-core.c 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/Makefile
View file @ 0f59185c
This diff is collapsed.
software/firmware/adc-x2/Kconfig 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/adc-x2/Makefile 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/adc-x2/TBuild 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/adc-x2/configs/mt_defconfig 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/adc-x2/trtl-memory.ld 0 → 120000
View file @ 0f59185c
This diff is collapsed.
software/firmware/adc-x2/wrtd-rt-adc-x2.c 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/adc/Makefile
View file @ 0f59185c
This diff is collapsed.
software/firmware/adc/configs/mt_defconfig
View file @ 0f59185c
This diff is collapsed.
software/firmware/adc/wrtd-adcin.c
View file @ 0f59185c
This diff is collapsed.
software/firmware/adc/wrtd-adcout.c
View file @ 0f59185c
This diff is collapsed.
software/firmware/adc/wrtd-rt-adc.c
View file @ 0f59185c
This diff is collapsed.
software/firmware/common/wrtd-rt-common.h
View file @ 0f59185c
This diff is collapsed.
software/firmware/fd-x2/Kconfig 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/fd-x2/Makefile 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/fd-x2/TBuild 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/fd-x2/configs/mt_defconfig 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/fd-x2/trtl-memory.ld 0 → 120000
View file @ 0f59185c
This diff is collapsed.
software/firmware/fd-x2/wrtd-rt-fd-x2.c 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/fd/Makefile
View file @ 0f59185c
This diff is collapsed.
software/firmware/fd/configs/mt_defconfig
View file @ 0f59185c
This diff is collapsed.
software/firmware/fd/fd-calibrate.c
View file @ 0f59185c
This diff is collapsed.
software/firmware/fd/wrtd-fd.c
View file @ 0f59185c
This diff is collapsed.
software/firmware/fd/wrtd-rt-fd.c
View file @ 0f59185c
This diff is collapsed.
software/firmware/tdc-x2/Kconfig 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/tdc-x2/Makefile 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/tdc-x2/TBuild 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/tdc-x2/configs/mt_defconfig 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/tdc-x2/trtl-memory.ld 0 → 120000
View file @ 0f59185c
This diff is collapsed.
software/firmware/tdc-x2/wrtd-rt-tdc-x2.c 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/firmware/tdc/Makefile
View file @ 0f59185c
This diff is collapsed.
software/firmware/tdc/configs/mt_defconfig
View file @ 0f59185c
This diff is collapsed.
software/firmware/tdc/hw/fmctdc-direct.h
View file @ 0f59185c
This diff is collapsed.
software/firmware/tdc/hw/tdc_regs.h
View file @ 0f59185c
This diff is collapsed.
software/firmware/tdc/wrtd-rt-tdc.c
View file @ 0f59185c
This diff is collapsed.
software/firmware/tdc/wrtd-tdc.c
View file @ 0f59185c
This diff is collapsed.
software/include/wrtd-common.h
View file @ 0f59185c
This diff is collapsed.
software/lib/.gitignore
View file @ 0f59185c
This diff is collapsed.
software/lib/Makefile
View file @ 0f59185c
This diff is collapsed.
software/lib/libwrtd-attributes.c
View file @ 0f59185c
This diff is collapsed.
software/lib/libwrtd-internal.c
View file @ 0f59185c
This diff is collapsed.
software/lib/libwrtd-private.h
View file @ 0f59185c
This diff is collapsed.
software/lib/libwrtd-reconfigure.c
View file @ 0f59185c
This diff is collapsed.
software/lib/libwrtd.c
View file @ 0f59185c
This diff is collapsed.
software/lib/libwrtd.h
View file @ 0f59185c
This diff is collapsed.
software/lib/python/PyWrtd/__init__.py 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/lib/python/setup.py
View file @ 0f59185c
This diff is collapsed.
software/tools/Makefile 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/tools/setup.py 0 → 100644
View file @ 0f59185c
This diff is collapsed.
software/udev/rules.d/71-trtl-wrtd.rules 0 → 100644
View file @ 0f59185c
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment