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Software for White Rabbit PTP Core
Commit 777d7061 authored by Michel Arruat's avatar Michel Arruat Committed by Adam Wujek
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tools:wr-streamer New test to program streamer wr core 

        This new test program is using ldevmap and lextest because it is
        interactive.
Signed-off-by: Michel Arruat's avatarMichel Arruat <michel.arruat@cern.ch>
parent e08116c9
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include/hw/wr-streamer.h 0 → 100644
View file @ 777d7061
/*
Register definitions for slave core: WR Transmission control, status and debug
* File : ./doc/wr_transmission.h
* Author : auto-generated by wbgen2 from wr_transmission_wb.wb
* Created : Wed May 3 10:58:23 2017
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WR_TRANSMISSION_WB_WB
#define __WBGEN2_REGDEFS_WR_TRANSMISSION_WB_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Statistics status and ctrl register */
/* definitions for field: Reset statistics in reg: Statistics status and ctrl register */
#define WR_TRANSMISSION_SSCR1_RST_STATS WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Reset tx seq id in reg: Statistics status and ctrl register */
#define WR_TRANSMISSION_SSCR1_RST_SEQ_ID WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Snapshot statistics in reg: Statistics status and ctrl register */
#define WR_TRANSMISSION_SSCR1_SNAPSHOT_STATS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Latency accumulator overflow in reg: Statistics status and ctrl register */
#define WR_TRANSMISSION_SSCR1_RX_LATENCY_ACC_OVERFLOW WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reset timestamp cycles in reg: Statistics status and ctrl register */
#define WR_TRANSMISSION_SSCR1_RST_TS_CYC_MASK WBGEN2_GEN_MASK(4, 28)
#define WR_TRANSMISSION_SSCR1_RST_TS_CYC_SHIFT 4
#define WR_TRANSMISSION_SSCR1_RST_TS_CYC_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WR_TRANSMISSION_SSCR1_RST_TS_CYC_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Statistics status and ctrl register */
/* definitions for field: Reset timestamp 32 LSB of TAI in reg: Statistics status and ctrl register */
#define WR_TRANSMISSION_SSCR2_RST_TS_TAI_LSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_TRANSMISSION_SSCR2_RST_TS_TAI_LSB_SHIFT 0
#define WR_TRANSMISSION_SSCR2_RST_TS_TAI_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_TRANSMISSION_SSCR2_RST_TS_TAI_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Tx statistics */
/* definitions for field: WR Streamer frame sent count in reg: Tx statistics */
#define WR_TRANSMISSION_TX_STAT_TX_SENT_CNT_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_TRANSMISSION_TX_STAT_TX_SENT_CNT_SHIFT 0
#define WR_TRANSMISSION_TX_STAT_TX_SENT_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_TRANSMISSION_TX_STAT_TX_SENT_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame received count in reg: Rx statistics */
#define WR_TRANSMISSION_RX_STAT1_RX_RCVD_CNT_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_TRANSMISSION_RX_STAT1_RX_RCVD_CNT_SHIFT 0
#define WR_TRANSMISSION_RX_STAT1_RX_RCVD_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_TRANSMISSION_RX_STAT1_RX_RCVD_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame loss count in reg: Rx statistics */
#define WR_TRANSMISSION_RX_STAT2_RX_LOSS_CNT_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_TRANSMISSION_RX_STAT2_RX_LOSS_CNT_SHIFT 0
#define WR_TRANSMISSION_RX_STAT2_RX_LOSS_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_TRANSMISSION_RX_STAT2_RX_LOSS_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency in reg: Rx statistics */
#define WR_TRANSMISSION_RX_STAT3_RX_LATENCY_MAX_MASK WBGEN2_GEN_MASK(0, 28)
#define WR_TRANSMISSION_RX_STAT3_RX_LATENCY_MAX_SHIFT 0
#define WR_TRANSMISSION_RX_STAT3_RX_LATENCY_MAX_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define WR_TRANSMISSION_RX_STAT3_RX_LATENCY_MAX_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency in reg: Rx statistics */
#define WR_TRANSMISSION_RX_STAT4_RX_LATENCY_MIN_MASK WBGEN2_GEN_MASK(0, 28)
#define WR_TRANSMISSION_RX_STAT4_RX_LATENCY_MIN_SHIFT 0
#define WR_TRANSMISSION_RX_STAT4_RX_LATENCY_MIN_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define WR_TRANSMISSION_RX_STAT4_RX_LATENCY_MIN_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency in reg: Rx statistics */
#define WR_TRANSMISSION_RX_STAT5_RX_LATENCY_ACC_LSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_TRANSMISSION_RX_STAT5_RX_LATENCY_ACC_LSB_SHIFT 0
#define WR_TRANSMISSION_RX_STAT5_RX_LATENCY_ACC_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_TRANSMISSION_RX_STAT5_RX_LATENCY_ACC_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency in reg: Rx statistics */
#define WR_TRANSMISSION_RX_STAT6_RX_LATENCY_ACC_MSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_TRANSMISSION_RX_STAT6_RX_LATENCY_ACC_MSB_SHIFT 0
#define WR_TRANSMISSION_RX_STAT6_RX_LATENCY_ACC_MSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_TRANSMISSION_RX_STAT6_RX_LATENCY_ACC_MSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency counter in reg: Rx statistics */
#define WR_TRANSMISSION_RX_STAT7_RX_LATENCY_ACC_CNT_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_TRANSMISSION_RX_STAT7_RX_LATENCY_ACC_CNT_SHIFT 0
#define WR_TRANSMISSION_RX_STAT7_RX_LATENCY_ACC_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_TRANSMISSION_RX_STAT7_RX_LATENCY_ACC_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer block loss count in reg: Rx statistics */
#define WR_TRANSMISSION_RX_STAT8_RX_LOST_BLOCK_CNT_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_TRANSMISSION_RX_STAT8_RX_LOST_BLOCK_CNT_SHIFT 0
#define WR_TRANSMISSION_RX_STAT8_RX_LOST_BLOCK_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_TRANSMISSION_RX_STAT8_RX_LOST_BLOCK_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Tx Config Reg 0 */
/* definitions for field: Ethertype in reg: Tx Config Reg 0 */
#define WR_TRANSMISSION_TX_CFG0_ETHERTYPE_MASK WBGEN2_GEN_MASK(0, 16)
#define WR_TRANSMISSION_TX_CFG0_ETHERTYPE_SHIFT 0
#define WR_TRANSMISSION_TX_CFG0_ETHERTYPE_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define WR_TRANSMISSION_TX_CFG0_ETHERTYPE_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Tx Config Reg 1 */
/* definitions for field: MAC Local LSB in reg: Tx Config Reg 1 */
#define WR_TRANSMISSION_TX_CFG1_MAC_LOCAL_LSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_TRANSMISSION_TX_CFG1_MAC_LOCAL_LSB_SHIFT 0
#define WR_TRANSMISSION_TX_CFG1_MAC_LOCAL_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_TRANSMISSION_TX_CFG1_MAC_LOCAL_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Tx Config Reg 2 */
/* definitions for field: MAC Local MSB in reg: Tx Config Reg 2 */
#define WR_TRANSMISSION_TX_CFG2_MAC_LOCAL_MSB_MASK WBGEN2_GEN_MASK(0, 16)
#define WR_TRANSMISSION_TX_CFG2_MAC_LOCAL_MSB_SHIFT 0
#define WR_TRANSMISSION_TX_CFG2_MAC_LOCAL_MSB_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define WR_TRANSMISSION_TX_CFG2_MAC_LOCAL_MSB_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Tx Config Reg 3 */
/* definitions for field: MAC Target LSB in reg: Tx Config Reg 3 */
#define WR_TRANSMISSION_TX_CFG3_MAC_TARGET_LSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_TRANSMISSION_TX_CFG3_MAC_TARGET_LSB_SHIFT 0
#define WR_TRANSMISSION_TX_CFG3_MAC_TARGET_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_TRANSMISSION_TX_CFG3_MAC_TARGET_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Tx Config Reg 4 */
/* definitions for field: MAC Target MSB in reg: Tx Config Reg 4 */
#define WR_TRANSMISSION_TX_CFG4_MAC_TARGET_MSB_MASK WBGEN2_GEN_MASK(0, 16)
#define WR_TRANSMISSION_TX_CFG4_MAC_TARGET_MSB_SHIFT 0
#define WR_TRANSMISSION_TX_CFG4_MAC_TARGET_MSB_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define WR_TRANSMISSION_TX_CFG4_MAC_TARGET_MSB_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Rx Config Reg 0 */
/* definitions for field: Ethertype in reg: Rx Config Reg 0 */
#define WR_TRANSMISSION_RX_CFG0_ETHERTYPE_MASK WBGEN2_GEN_MASK(0, 16)
#define WR_TRANSMISSION_RX_CFG0_ETHERTYPE_SHIFT 0
#define WR_TRANSMISSION_RX_CFG0_ETHERTYPE_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define WR_TRANSMISSION_RX_CFG0_ETHERTYPE_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Accept Broadcast in reg: Rx Config Reg 0 */
#define WR_TRANSMISSION_RX_CFG0_ACCEPT_BROADCAST WBGEN2_GEN_MASK(16, 1)
/* definitions for field: Filter Remote in reg: Rx Config Reg 0 */
#define WR_TRANSMISSION_RX_CFG0_FILTER_REMOTE WBGEN2_GEN_MASK(17, 1)
/* definitions for register: Rx Config Reg 1 */
/* definitions for field: MAC Local LSB in reg: Rx Config Reg 1 */
#define WR_TRANSMISSION_RX_CFG1_MAC_LOCAL_LSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_TRANSMISSION_RX_CFG1_MAC_LOCAL_LSB_SHIFT 0
#define WR_TRANSMISSION_RX_CFG1_MAC_LOCAL_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_TRANSMISSION_RX_CFG1_MAC_LOCAL_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx Config Reg 2 */
/* definitions for field: MAC Local MSB in reg: Rx Config Reg 2 */
#define WR_TRANSMISSION_RX_CFG2_MAC_LOCAL_MSB_MASK WBGEN2_GEN_MASK(0, 16)
#define WR_TRANSMISSION_RX_CFG2_MAC_LOCAL_MSB_SHIFT 0
#define WR_TRANSMISSION_RX_CFG2_MAC_LOCAL_MSB_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define WR_TRANSMISSION_RX_CFG2_MAC_LOCAL_MSB_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Rx Config Reg 3 */
/* definitions for field: MAC Remote LSB in reg: Rx Config Reg 3 */
#define WR_TRANSMISSION_RX_CFG3_MAC_REMOTE_LSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_TRANSMISSION_RX_CFG3_MAC_REMOTE_LSB_SHIFT 0
#define WR_TRANSMISSION_RX_CFG3_MAC_REMOTE_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_TRANSMISSION_RX_CFG3_MAC_REMOTE_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx Config Reg 4 */
/* definitions for field: MAC Remote MSB in reg: Rx Config Reg 4 */
#define WR_TRANSMISSION_RX_CFG4_MAC_REMOTE_MSB_MASK WBGEN2_GEN_MASK(0, 16)
#define WR_TRANSMISSION_RX_CFG4_MAC_REMOTE_MSB_SHIFT 0
#define WR_TRANSMISSION_RX_CFG4_MAC_REMOTE_MSB_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define WR_TRANSMISSION_RX_CFG4_MAC_REMOTE_MSB_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Rx Config Reg 5 */
/* definitions for field: Fixed Latency in reg: Rx Config Reg 5 */
#define WR_TRANSMISSION_RX_CFG5_FIXED_LATENCY_MASK WBGEN2_GEN_MASK(0, 28)
#define WR_TRANSMISSION_RX_CFG5_FIXED_LATENCY_SHIFT 0
#define WR_TRANSMISSION_RX_CFG5_FIXED_LATENCY_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define WR_TRANSMISSION_RX_CFG5_FIXED_LATENCY_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: TxRx Config Override */
/* definitions for field: Tx Ethertype in reg: TxRx Config Override */
#define WR_TRANSMISSION_CFG_OR_TX_ETHTYPE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Tx MAC Local in reg: TxRx Config Override */
#define WR_TRANSMISSION_CFG_OR_TX_MAC_LOC WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Tx MAC Target in reg: TxRx Config Override */
#define WR_TRANSMISSION_CFG_OR_TX_MAC_TAR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Rx Ethertype in reg: TxRx Config Override */
#define WR_TRANSMISSION_CFG_OR_RX_ETHERTYPE WBGEN2_GEN_MASK(16, 1)
/* definitions for field: Rx MAC Local in reg: TxRx Config Override */
#define WR_TRANSMISSION_CFG_OR_RX_MAC_LOC WBGEN2_GEN_MASK(17, 1)
/* definitions for field: Rx MAC Remote in reg: TxRx Config Override */
#define WR_TRANSMISSION_CFG_OR_RX_MAC_REM WBGEN2_GEN_MASK(18, 1)
/* definitions for field: Rx Accept Broadcast in reg: TxRx Config Override */
#define WR_TRANSMISSION_CFG_OR_RX_ACC_BROADCAST WBGEN2_GEN_MASK(19, 1)
/* definitions for field: Rx Filter Remote in reg: TxRx Config Override */
#define WR_TRANSMISSION_CFG_OR_RX_FTR_REMOTE WBGEN2_GEN_MASK(20, 1)
/* definitions for field: Rx Fixed Latency in reg: TxRx Config Override */
#define WR_TRANSMISSION_CFG_OR_RX_FIX_LAT WBGEN2_GEN_MASK(21, 1)
/* definitions for register: DBG Control register */
/* definitions for field: Debug Tx (0) or Rx (1) in reg: DBG Control register */
#define WR_TRANSMISSION_DBG_CTRL_MUX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Debug Start byte in reg: DBG Control register */
#define WR_TRANSMISSION_DBG_CTRL_START_BYTE_MASK WBGEN2_GEN_MASK(8, 8)
#define WR_TRANSMISSION_DBG_CTRL_START_BYTE_SHIFT 8
#define WR_TRANSMISSION_DBG_CTRL_START_BYTE_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WR_TRANSMISSION_DBG_CTRL_START_BYTE_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for register: DBG Data */
/* definitions for register: DBG RX_BVALUE */
/* definitions for register: DBG tx bvalue */
/* definitions for register: Test value */
/* definitions for field: DUMMY value to read in reg: Test value */
#define WR_TRANSMISSION_DUMMY_DUMMY_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_TRANSMISSION_DUMMY_DUMMY_SHIFT 0
#define WR_TRANSMISSION_DUMMY_DUMMY_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_TRANSMISSION_DUMMY_DUMMY_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
PACKED struct WR_TRANSMISSION_WB {
/* [0x0]: REG Statistics status and ctrl register */
uint32_t SSCR1;
/* [0x4]: REG Statistics status and ctrl register */
uint32_t SSCR2;
/* [0x8]: REG Tx statistics */
uint32_t TX_STAT;
/* [0xc]: REG Rx statistics */
uint32_t RX_STAT1;
/* [0x10]: REG Rx statistics */
uint32_t RX_STAT2;
/* [0x14]: REG Rx statistics */
uint32_t RX_STAT3;
/* [0x18]: REG Rx statistics */
uint32_t RX_STAT4;
/* [0x1c]: REG Rx statistics */
uint32_t RX_STAT5;
/* [0x20]: REG Rx statistics */
uint32_t RX_STAT6;
/* [0x24]: REG Rx statistics */
uint32_t RX_STAT7;
/* [0x28]: REG Rx statistics */
uint32_t RX_STAT8;
/* [0x2c]: REG Tx Config Reg 0 */
uint32_t TX_CFG0;
/* [0x30]: REG Tx Config Reg 1 */
uint32_t TX_CFG1;
/* [0x34]: REG Tx Config Reg 2 */
uint32_t TX_CFG2;
/* [0x38]: REG Tx Config Reg 3 */
uint32_t TX_CFG3;
/* [0x3c]: REG Tx Config Reg 4 */
uint32_t TX_CFG4;
/* [0x40]: REG Rx Config Reg 0 */
uint32_t RX_CFG0;
/* [0x44]: REG Rx Config Reg 1 */
uint32_t RX_CFG1;
/* [0x48]: REG Rx Config Reg 2 */
uint32_t RX_CFG2;
/* [0x4c]: REG Rx Config Reg 3 */
uint32_t RX_CFG3;
/* [0x50]: REG Rx Config Reg 4 */
uint32_t RX_CFG4;
/* [0x54]: REG Rx Config Reg 5 */
uint32_t RX_CFG5;
/* [0x58]: REG TxRx Config Override */
uint32_t CFG;
/* [0x5c]: REG DBG Control register */
uint32_t DBG_CTRL;
/* [0x60]: REG DBG Data */
uint32_t DBG_DATA;
/* [0x64]: REG DBG RX_BVALUE */
uint32_t DBG_RX_BVALUE;
/* [0x68]: REG DBG tx bvalue */
uint32_t DBG_TX_BVALUE;
/* [0x6c]: REG Test value */
uint32_t DUMMY;
};
#endif
tools/Makefile
View file @ 777d7061
......@@ -2,16 +2,18 @@ EB ?= no
SDBFS ?= no
SUPPORT_CERN_VMEBRIDGE ?= n
CFLAGS = -Wall -ggdb -I../include -I../liblinux
CFLAGS = -Wall -ggdb -I../include -I../liblinux -I../liblinux/extest
ifeq ($(SUPPORT_CERN_VMEBRIDGE), y)
CFLAGS += -DSUPPORT_CERN_VMEBRIDGE
endif
LDFLAGS = -lutil -L../liblinux -ldevmap
LDFLAGS = -lutil -L../liblinux -ldevmap -L../liblinux/extest -lextest
LDFLAGS += -lreadline
ALL = genraminit genramvhd genrammif
ALL += wrpc-w1-read wrpc-w1-write
ALL += pfilter-builder
ALL += wrpc-dump mapper
ALL += wrpc-vuart
ALL += wr-streamer
ifneq ($(EB),no)
ALL += eb-w1-write
......@@ -53,6 +55,9 @@ wrpc-dump: wrpc-dump.c dump-info-host.o
$^ -o $@ \
-D__GIT_VER__="\"$(GIT_VER)\"" -D__GIT_USR__="\"$(GIT_USR)\""
wr-streamer: wr-streamer.c
$(CC) $(CFLAGS) $^ $(LDFLAGS) -o $@
wrpc-vuart: wrpc-vuart.c
$(CC) $(CFLAGS) -Werror $^ $(LDFLAGS) -o $@
......
tools/wr-streamer.c 0 → 100644
View file @ 777d7061
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <unistd.h>
#include <getopt.h>
#include <errno.h>
#include <time.h>
#include <libdevmap.h>
#include <extest.h>
#include <hw/wr-streamer.h>
static struct mapping_desc *wrstm = NULL;
int read_all_stats(struct cmd_desc *cmdd, struct atom *atoms)
{
uint32_t max_latency_raw= 0, min_latency_raw=0;
double max_latency= 0, min_latency=0;
uint32_t rx_cnt= 0, tx_cnt=0, rx_cnt_lost_fr=0, rx_cnt_lost_blk=0;
uint64_t latency_acc =0;
uint32_t latency_acc_lsb=0, latency_acc_msb=0, latency_cnt=0, val=0;
int overflow=0;
double latency_avg=0;
volatile struct WR_TRANSMISSION_WB *ptr =
(volatile struct WR_TRANSMISSION_WB *)wrstm->base;
if (atoms == (struct atom *)VERBOSE_HELP) {
printf("%s - %s\n", cmdd->name, cmdd->help);
return 1;
}
//snapshot stats
ptr->SSCR1 = WR_TRANSMISSION_SSCR1_SNAPSHOT_STATS;
// min/max
max_latency_raw = ptr->RX_STAT3;
max_latency = (WR_TRANSMISSION_RX_STAT3_RX_LATENCY_MAX_R(max_latency_raw)*8)/1000.0;
min_latency_raw = ptr->RX_STAT4;
min_latency = (WR_TRANSMISSION_RX_STAT4_RX_LATENCY_MIN_R(min_latency_raw)*8)/1000.0;
//cnts
tx_cnt = ptr->TX_STAT;
rx_cnt = ptr->RX_STAT1;
rx_cnt_lost_fr = ptr->RX_STAT2;
rx_cnt_lost_blk = ptr->RX_STAT8;
//read values
latency_acc_lsb = ptr->RX_STAT5;
latency_acc_msb = ptr->RX_STAT6;
latency_cnt = ptr->RX_STAT7;
val = ptr->RX_STAT7;
overflow = (WR_TRANSMISSION_SSCR1_RX_LATENCY_ACC_OVERFLOW & val) != 0;
//put it all together
latency_acc = (((uint64_t)latency_acc_msb) << 32) | latency_acc_lsb;
latency_avg = (((double)latency_acc)*8/1000)/(double)latency_cnt;
//release snapshot
ptr->SSCR1 = 0;
fprintf(stderr, "Latency [us] : min=%10g max=%10g avg =%10g "
"(0x%x, 0x%x, %lld=%u << 32 | %u)*8/1000 us, cnt=%u)\n",
min_latency, max_latency, latency_avg, min_latency_raw,
max_latency_raw, (long long)latency_acc, latency_acc_msb,
latency_acc_lsb, latency_cnt);
fprintf(stderr, "Frames [number]: tx =%10u rx =%10u lost=%10u "
"(lost blocks%5u)\n",
tx_cnt, rx_cnt, rx_cnt_lost_fr,rx_cnt_lost_blk);
return 1;
}
#define LEAP_SECONDS 37
int read_reset_time(struct cmd_desc *cmdd, struct atom *atoms)
{
uint32_t val=0;
int days=0, hours=0, minutes=0, seconds;
double reset_time_elapsed=0;
time_t cur_time;
time_t res_time_sec;
volatile struct WR_TRANSMISSION_WB *ptr =
(volatile struct WR_TRANSMISSION_WB *)wrstm->base;
if (atoms == (struct atom *)VERBOSE_HELP) {
printf("%s - %s\n", cmdd->name, cmdd->help);
return 1;
}
val = ptr->SSCR2;
res_time_sec = (time_t)(WR_TRANSMISSION_SSCR2_RST_TS_TAI_LSB_R(val) +
LEAP_SECONDS);//to UTC
cur_time = time(NULL);
reset_time_elapsed = difftime(cur_time,res_time_sec);
days = reset_time_elapsed/(60*60*24);
hours = (reset_time_elapsed-days*60*60*24)/(60*60);
minutes = (reset_time_elapsed-days*60*60*24-hours*60*60)/(60);
seconds = (reset_time_elapsed-days*60*60*24-hours*60*60-minutes*60);
fprintf(stderr, "Time elapsed from reset: %d days, %d h, %d m, %d s; Reseted on %s\n",
days, hours, minutes, seconds, asctime(localtime(&res_time_sec)));
return 1;
}
int reset_counters(struct cmd_desc *cmdd, struct atom *atoms)
{
return 1;
}
int reset_seqid(struct cmd_desc *cmdd, struct atom *atoms)
{
return 1;
}
int set_tx_ethertype(struct cmd_desc *cmdd, struct atom *atoms)
{
return 1;
}
int set_tx_local_mac(struct cmd_desc *cmdd, struct atom *atoms)
{
return 1;
}
int set_tx_remote_mac(struct cmd_desc *cmdd, struct atom *atoms)
{
return 1;
}
int set_rx_ethertype(struct cmd_desc *cmdd, struct atom *atoms)
{
return 1;
}
int set_rx_local_mac(struct cmd_desc *cmdd, struct atom *atoms)
{
return 1;
}
int set_rx_remote_mac(struct cmd_desc *cmdd, struct atom *atoms)
{
return 1;
}
int get_set_latency(struct cmd_desc *cmdd, struct atom *atoms)
{
return 1;
}
enum wrstm_cmd_id{
WRSTM_CMD_STATS = CMD_USR,
WRSTM_CMD_RESET,
WRSTM_CMD_RESET_CNTS,
WRSTM_CMD_RESET_SEQID,
WRSTM_CMD_TX_ETHERTYPE,
WRSTM_CMD_TX_LOC_MAC,
WRSTM_CMD_TX_REM_MAC,
WRSTM_CMD_RX_ETHERTYPE,
WRSTM_CMD_RX_LOC_MAC,
WRSTM_CMD_RX_REM_MAC,
WRSTM_CMD_LATENCY,
// WRSTM_CMD_DBG_BYTE,
// WRSTM_CMD_DBG_MUX,
// WRSTM_CMD_DBG_VAL,
WRSTM_CMD_LAST,
};
#define WRSTM_CMD_NB WRSTM_CMD_LAST - CMD_USR
struct cmd_desc wrstm_cmd[WRSTM_CMD_NB + 1] = {
{ 1, WRSTM_CMD_STATS, "stats", "show all streamers statistics",
"", 0, read_all_stats},
{ 1, WRSTM_CMD_RESET, "reset",
"show time of the latest reset / time elapsed since then", "", 0,
read_reset_time},
{ 1, WRSTM_CMD_RESET_CNTS, "resetcnt",
"reset tx/rx/lost counters and avg/min/max latency values", "", 0,
reset_counters},
{ 1, WRSTM_CMD_RESET_SEQID, "resetseqid",
"reset sequence ID of the tx streamer", "", 0, reset_seqid},
{ 1, WRSTM_CMD_TX_ETHERTYPE, "txether",
"set TX ethertype", "ethertype", 1, set_tx_ethertype},
{ 1, WRSTM_CMD_TX_LOC_MAC, "txlocmac",
"set TX Local MAC addres", "mac", 1, set_tx_local_mac},
{ 1, WRSTM_CMD_TX_REM_MAC, "txremmac",
"set TX Target MAC address", "mac", 1, set_tx_remote_mac},
{ 1, WRSTM_CMD_RX_ETHERTYPE, "rxether",
"set RX ethertype", "ethertype", 1, set_rx_ethertype},
{ 1, WRSTM_CMD_RX_LOC_MAC, "rxlocmac",
"set RX Local MAC addres", "mac", 1, set_rx_local_mac},
{ 1, WRSTM_CMD_RX_REM_MAC, "rxremmac",
"set RX Remote MAC address", "mac", 1, set_rx_remote_mac},
{ 1, WRSTM_CMD_LATENCY, "lat",
"get/set config of fixed latency in integer [us] (-1 to disable)",
"[latency]", 0, get_set_latency},
// { 1, WRSTM_CMD_DBG_BYTE, "dbgbyte",
// "set which byte of the rx or tx frame should be snooped", "byte", 1,},
// { 1, WRSTM_CMD_DBG_MUX, "dbgdir",
// "set whether tx or rx frames should be snooped", "dir", 1,},
// { 1, WRSTM_CMD_DBG_VAL, "dbgword",
// "read the snooped 32-bit value", "", 0,},
{0, },
};
static void wrstm_help(char *prog)
{
fprintf(stderr, "%s [options]\n", prog);
fprintf(stderr, "%s\n", dev_mapping_help());
}
static void sig_hndl()
{
// Signal occured: free resource and exit
fprintf(stderr, "Handle signal: free resource and exit.\n");
dev_unmap(wrstm);
exit(1);
}
int main(int argc, char *argv[])
{
int ret;
struct mapping_args *map_args;
map_args = dev_parse_mapping_args(argc, argv);
if (!map_args) {
wrstm_help(argv[0]);
return -1;
}
wrstm = dev_map(map_args, sizeof(struct WR_TRANSMISSION_WB));
if (!wrstm) {
fprintf(stderr, "%s: wrstm mmap() failed: %s\n", argv[0],
strerror(errno));
free(map_args);
return -1;
}
ret = extest_register_user_cmd(wrstm_cmd, WRSTM_CMD_NB);
if (ret) {
dev_unmap(wrstm);
return -1;
}
/* execute command loop */
ret = extest_run("wrtsm", sig_hndl);
dev_unmap(wrstm);
return (ret) ? -1 : 0;
}
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