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wr2rf-vme
Commit cfa9dbec authored by John Gill's avatar John Gill
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RF changes for timestamps, etc

parent fe7a8fb1
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Showing with 345 additions and 73 deletions
hdl/rtl/registers/trigunit_regs.cheby
View file @ cfa9dbec
......@@ -265,6 +265,34 @@ memory-map:
description: value
range: 4-0
preset: 0x0
- reg:
name: TS_FirstTrigTAIsec
description: "Timestamp TAI seconds of the first VTU output trigger after a start pulse"
comment:
width: 64
type: unsigned
access: ro
- reg:
name: TS_FirstTrigTAIcycles
description: "Timestamp TAI cycles of the first VTU output trigger after a start pulse"
comment:
width: 32
type: unsigned
access: ro
- reg:
name: TS_LastTrigTAIsec
description: "Timestamp TAI seconds of the last VTU output trigger"
comment:
width: 64
type: unsigned
access: ro
- reg:
name: TS_LastTrigTAIcycles
description: "Timestamp TAI cycles of the last VTU output trigger"
comment:
width: 32
type: unsigned
access: ro
- submap:
name: trigdiag
filename: vtudiag_regs.cheby
......
hdl/rtl/registers/trigunit_regs.vhd
View file @ cfa9dbec
-- Do not edit. Generated on Tue Sep 07 11:28:03 2021 by jgill
-- Do not edit. Generated on Mon Mar 13 15:51:07 2023 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd
......@@ -84,6 +84,18 @@ entity trigunit_regs is
-- value
trigODelay_delay_o : out std_logic_vector(4 downto 0);
-- Timestamp TAI seconds of the first VTU output trigger after a start pulse
TS_FirstTrigTAIsec_i : in std_logic_vector(63 downto 0);
-- Timestamp TAI cycles of the first VTU output trigger after a start pulse
TS_FirstTrigTAIcycles_i : in std_logic_vector(31 downto 0);
-- Timestamp TAI seconds of the last VTU output trigger
TS_LastTrigTAIsec_i : in std_logic_vector(63 downto 0);
-- Timestamp TAI cycles of the last VTU output trigger
TS_LastTrigTAIcycles_i : in std_logic_vector(31 downto 0);
-- Control register
-- Enable the unit
trigdiag_control_enable_o : out std_logic;
......@@ -359,6 +371,14 @@ begin
end if;
end process;
-- Register TS_FirstTrigTAIsec
-- Register TS_FirstTrigTAIcycles
-- Register TS_LastTrigTAIsec
-- Register TS_LastTrigTAIcycles
-- Register trigdiag_control
trigdiag_control_enable_o <= trigdiag_control_enable_reg;
trigdiag_control_window_o <= trigdiag_control_window_reg;
......@@ -546,7 +566,63 @@ begin
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "1001" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg TS_FirstTrigTAIsec
wr_ack_int <= wr_req_d0;
when "01" =>
-- Reg TS_FirstTrigTAIsec
wr_ack_int <= wr_req_d0;
when "10" =>
-- Reg TS_FirstTrigTAIsec
wr_ack_int <= wr_req_d0;
when "11" =>
-- Reg TS_FirstTrigTAIsec
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "1010" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg TS_FirstTrigTAIcycles
wr_ack_int <= wr_req_d0;
when "01" =>
-- Reg TS_FirstTrigTAIcycles
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "1011" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg TS_LastTrigTAIsec
wr_ack_int <= wr_req_d0;
when "01" =>
-- Reg TS_LastTrigTAIsec
wr_ack_int <= wr_req_d0;
when "10" =>
-- Reg TS_LastTrigTAIsec
wr_ack_int <= wr_req_d0;
when "11" =>
-- Reg TS_LastTrigTAIsec
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "1100" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg TS_LastTrigTAIcycles
wr_ack_int <= wr_req_d0;
when "01" =>
-- Reg TS_LastTrigTAIcycles
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "1110" =>
case wr_adr_d0(2 downto 2) is
when "0" =>
case wr_adr_d0(1 downto 1) is
......@@ -574,7 +650,7 @@ begin
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "1011" =>
when "1111" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg trigdiag_counter
......@@ -591,7 +667,7 @@ begin
end process;
-- Process for read requests.
process (adr_int, rd_req_int, status_wrongWvalue_i, status_wrongHTvalue_i, status_wrongBvalue_i, status_running_i, status_startReady_i, status_missReady_i, status_missValid_i, status_idle_i, status_started_i, control_vtuReset_reg, configOffline_valid_i, configOffline_htSwitchingEnable_reg, configOffline_mode_reg, bValueOffline_reg, htValueOffline_reg, wValueOffline_reg, configOnline_htSwitchingEnable_i, configOnline_mode_i, bValueOnline_i, htValueOnline_i, wValueOnline_i, trigOHCDelay_set_reg, trigODelay_delay_reg, trigdiag_control_window_reg, trigdiag_control_enable_reg, trigdiag_generation_i, trigdiag_freq_i, trigdiag_counter_i) begin
process (adr_int, rd_req_int, status_wrongWvalue_i, status_wrongHTvalue_i, status_wrongBvalue_i, status_running_i, status_startReady_i, status_missReady_i, status_missValid_i, status_idle_i, status_started_i, control_vtuReset_reg, configOffline_valid_i, configOffline_htSwitchingEnable_reg, configOffline_mode_reg, bValueOffline_reg, htValueOffline_reg, wValueOffline_reg, configOnline_htSwitchingEnable_i, configOnline_mode_i, bValueOnline_i, htValueOnline_i, wValueOnline_i, trigOHCDelay_set_reg, trigODelay_delay_reg, TS_FirstTrigTAIsec_i, TS_FirstTrigTAIcycles_i, TS_LastTrigTAIsec_i, TS_LastTrigTAIcycles_i, trigdiag_control_window_reg, trigdiag_control_enable_reg, trigdiag_generation_i, trigdiag_freq_i, trigdiag_counter_i) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
case adr_int(6 downto 3) is
......@@ -783,7 +859,75 @@ begin
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "1001" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg TS_FirstTrigTAIsec
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= TS_FirstTrigTAIsec_i(63 downto 48);
when "01" =>
-- Reg TS_FirstTrigTAIsec
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= TS_FirstTrigTAIsec_i(47 downto 32);
when "10" =>
-- Reg TS_FirstTrigTAIsec
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= TS_FirstTrigTAIsec_i(31 downto 16);
when "11" =>
-- Reg TS_FirstTrigTAIsec
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= TS_FirstTrigTAIsec_i(15 downto 0);
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "1010" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg TS_FirstTrigTAIcycles
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= TS_FirstTrigTAIcycles_i(31 downto 16);
when "01" =>
-- Reg TS_FirstTrigTAIcycles
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= TS_FirstTrigTAIcycles_i(15 downto 0);
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "1011" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg TS_LastTrigTAIsec
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= TS_LastTrigTAIsec_i(63 downto 48);
when "01" =>
-- Reg TS_LastTrigTAIsec
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= TS_LastTrigTAIsec_i(47 downto 32);
when "10" =>
-- Reg TS_LastTrigTAIsec
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= TS_LastTrigTAIsec_i(31 downto 16);
when "11" =>
-- Reg TS_LastTrigTAIsec
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= TS_LastTrigTAIsec_i(15 downto 0);
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "1100" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg TS_LastTrigTAIcycles
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= TS_LastTrigTAIcycles_i(31 downto 16);
when "01" =>
-- Reg TS_LastTrigTAIcycles
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= TS_LastTrigTAIcycles_i(15 downto 0);
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "1110" =>
case adr_int(2 downto 2) is
when "0" =>
case adr_int(1 downto 1) is
......@@ -817,7 +961,7 @@ begin
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "1011" =>
when "1111" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg trigdiag_counter
......
hdl/rtl/registers/wr2rf_init_rf_regs.vhd
View file @ cfa9dbec
-- Do not edit. Generated on Tue Sep 07 11:28:03 2021 by jgill
-- Do not edit. Generated on Mon Mar 13 15:51:08 2023 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd
......
hdl/rtl/registers/wr2rf_rfnco_regs.vhd
View file @ cfa9dbec
-- Do not edit. Generated on Tue Sep 07 11:28:04 2021 by jgill
-- Do not edit. Generated on Mon Mar 13 15:51:08 2023 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i RFNCO.cheby --gen-hdl
......
hdl/rtl/registers/wr2rf_rftrigger_regs.vhd
View file @ cfa9dbec
-- Do not edit. Generated on Tue Sep 07 11:28:03 2021 by jgill
-- Do not edit. Generated on Mon Mar 13 15:51:08 2023 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
......
hdl/rtl/registers/wr2rf_vme_regs.vhd
View file @ cfa9dbec
-- Do not edit. Generated on Tue Sep 07 11:28:05 2021 by jgill
-- Do not edit. Generated on Mon Mar 13 15:51:09 2023 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
......
hdl/rtl/vtu_blk.vhd
View file @ cfa9dbec
......@@ -49,6 +49,10 @@ entity vtu_blk is
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- TAI
tm_tai_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
-- RF clock (~200Mhz) for serdes
clk_rf_io_i : in std_logic;
......@@ -180,6 +184,16 @@ architecture rtl of vtu_blk is
signal clk_rf_io_n : std_logic;
signal vtu_trig_redge : std_logic;
signal vtu_trig_redge_r : std_logic;
signal vtu_trig_redge_sys : std_logic;
signal last_vtu_trig_tai_sec_r : std_logic_vector(63 downto 0);
signal last_vtu_trig_tai_cycles_r : std_logic_vector(31 downto 0);
signal first_vtu_trig_tai_sec_r : std_logic_vector(63 downto 0);
signal first_vtu_trig_tai_cycles_r : std_logic_vector(31 downto 0);
signal first_vtu_trig_active : std_logic;
signal first_vtu_trig_active_r : std_logic;
signal sync_data_out_clean : std_logic_vector(7 downto 0);
signal sync_data_out_clean_r : std_logic_vector(7 downto 0);
signal sync_data_x16_nohc : std_logic_vector(15 downto 0);
......@@ -187,6 +201,7 @@ architecture rtl of vtu_blk is
signal sync_data_x16 : std_logic_vector(15 downto 0);
signal vtu_clk_r : std_logic;
signal sync_data_oserdes : std_logic_vector(7 downto 0);
signal sync_data_oserdes_r : std_logic_vector(7 downto 0);
signal clk_vtu_hold_delay_n : std_logic;
signal clk_vtu_hold_delay : std_logic;
attribute dont_touch : string;
......@@ -222,20 +237,17 @@ begin
clk_i => clk_sys_i,
rst_n_a_i => rst_sys_n,
d_i => start_i,
q_o => start_sys
);
q_o => start_sys );
inst_start_edge: entity work.gc_edge_detect
generic map (
g_async_rst => False,
g_pulse_edge => "positive",
g_clock_edge => "positive"
)
g_clock_edge => "positive" )
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n,
data_i => start_sys,
pulse_o => start_pulse_sys
);
pulse_o => start_pulse_sys );
-- Synchronizer from the external/soft start to the start for VTU.
inst_start_psync: entity work.gc_pulse_synchronizer2
port map (
......@@ -246,8 +258,7 @@ begin
d_ready_o => start_ready,
d_ack_p_o => start_ack,
d_p_i => start_pulse_2,
q_p_o => vtu_start
);
q_p_o => vtu_start );
-- FIXME: add a miss flag for soft_stop ?
inst_softstop_psync: entity work.gc_pulse_synchronizer2
......@@ -518,6 +529,11 @@ begin
trigOHCDelay_set_o => sys_trig_delay_hc,
trigODelay_delay_o => sys_trig_odelay,
TS_FirstTrigTAIsec_i => first_vtu_trig_tai_sec_r,
TS_FirstTrigTAIcycles_i => first_vtu_trig_tai_cycles_r,
TS_LastTrigTAIsec_i => last_vtu_trig_tai_sec_r,
TS_LastTrigTAIcycles_i => last_vtu_trig_tai_cycles_r,
trigdiag_control_window_o => diag_window,
trigdiag_control_enable_o => diag_enable,
trigdiag_generation_i => diag_generation,
......@@ -728,6 +744,51 @@ begin
sync_data_oserdes <= sync_data_out_clean;
end generate;
-- find a rising edge in the VTU output
vtu_trig_redge <= '1' when ((sync_data_oserdes_r(0) = '0' and sync_data_oserdes(7) = '1') or
(sync_data_oserdes(7) = '0' and sync_data_oserdes(6) = '1') or
(sync_data_oserdes(6) = '0' and sync_data_oserdes(5) = '1') or
(sync_data_oserdes(5) = '0' and sync_data_oserdes(4) = '1') or
(sync_data_oserdes(4) = '0' and sync_data_oserdes(3) = '1') or
(sync_data_oserdes(3) = '0' and sync_data_oserdes(2) = '1') or
(sync_data_oserdes(2) = '0' and sync_data_oserdes(1) = '1') or
(sync_data_oserdes(1) = '0' and sync_data_oserdes(0) = '1')) else '0';
process (clk_vtu_x2_i) is
begin
if (rising_edge(clk_vtu_x2_i)) then
sync_data_oserdes_r <= sync_data_oserdes;
vtu_trig_redge_r <= vtu_trig_redge;
end if;
end process;
inst_redge_sync: entity work.gc_sync
port map (
clk_i => clk_sys_i,
rst_n_a_i => rst_sys_n,
d_i => vtu_trig_redge_r,
q_o => vtu_trig_redge_sys);
first_vtu_trig_active <= '1' when start_pulse_2 = '1' else
'0' when vtu_trig_redge_sys = '1' else first_vtu_trig_active_r;
process (clk_sys_i) is
begin
if (rising_edge(clk_sys_i)) then
if vtu_trig_redge_sys = '1' then
last_vtu_trig_tai_sec_r <= X"000000" & tm_tai_i;
last_vtu_trig_tai_cycles_r <= X"0" & tm_cycles_i;
if (first_vtu_trig_active_r = '1') then
first_vtu_trig_tai_sec_r <= X"000000" & tm_tai_i;
first_vtu_trig_tai_cycles_r <= X"0" & tm_cycles_i;
end if;
first_vtu_trig_active_r <= first_vtu_trig_active;
end if;
end if;
end process;
-- determine if there was a rising edge in the trigger output...
inst_trig_OSERDESE2 : OSERDESE2
generic map (
DATA_RATE_OQ => g_hc_string, -- DDR, SDR
......
hdl/rtl/wr2rf_regs_core.vhd
View file @ cfa9dbec
......@@ -350,8 +350,8 @@ begin
init_hwinfo_ident_jtagRemoteDisable_i => '1',
init_hwinfo_ident_extendedID_i => "0000000",
init_hwinfo_ident_cardID_i => x"56",
init_hwinfo_firmwareVersion_i => x"0000_15_00",
init_hwinfo_memMapVersion_i => x"0000_15_00",
init_hwinfo_firmwareVersion_i => x"0000_16_00",
init_hwinfo_memMapVersion_i => x"0000_16_00",
init_hwinfo_echo_echo_o => open,
init_fw_update_i => wb_fw_update_in,
......
hdl/rtl/wr2rf_rftrigger.vhd
View file @ cfa9dbec
......@@ -52,6 +52,10 @@ entity wr2rf_rftrigger is
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- TAI
tm_tai_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
-- Pulse from the Reset/sync logic.
rf_t1_sync_i : in std_logic;
rf_t1_sync_p_o : inout std_logic;
......@@ -420,6 +424,8 @@ begin
rst_serdes_i => t1_rst_vtu_pulse_r,
wb_i => t1_wb_in,
wb_o => t1_wb_out,
tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i,
clk_rf_io_i => rf_clk_io,
clk_rf_i => clk_rf,
......@@ -471,6 +477,8 @@ begin
rst_serdes_i => t2_rst_vtu_pulse_r,
wb_i => t2_wb_in,
wb_o => t2_wb_out,
tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i,
clk_rf_io_i => rf_clk_io,
clk_rf_i => clk_rf,
......
hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ cfa9dbec
......@@ -43,7 +43,7 @@ entity wr2rf_vme is
generic (
g_simulation : integer := 0;
g_dpram_size : integer := 131072/4;
g_dpram_initf : string := "../../../../dependencies/wrpc-sw/wrc-wr2rf-enabled-snmp-and-auxdiags.bram";
g_dpram_initf : string := "../../../../dependencies/wrpc-sw-file/wrc-wr2rf-enabled-snmp-and-auxdiags.bram";
-- g_dpram_initf : string := "";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......@@ -1363,6 +1363,8 @@ begin
iodelay_reset_i => iodelay_reset,
wb_i => wb_rf1_vtus_out,
wb_o => wb_rf1_vtus_in,
tm_tai_i => tm_tai,
tm_cycles_i => tm_cycles,
rf_t1_sync_i => nco_reset_rf1_trig1,
rf_t1_sync_cdelay_i => rf1_t1_sync_cdelay,
......@@ -1415,6 +1417,8 @@ begin
iodelay_reset_i => iodelay_reset,
wb_i => wb_rf2_vtus_out,
wb_o => wb_rf2_vtus_in,
tm_tai_i => tm_tai,
tm_cycles_i => tm_cycles,
rf_t1_sync_i => nco_reset_rf2_trig1,
rf_t1_sync_cdelay_i => rf2_t1_sync_cdelay,
......
software/include/trigunit_regs.h
View file @ cfa9dbec
......@@ -64,8 +64,20 @@
#define TRIGUNIT_REGS_TRIGODELAY_DELAY_MASK 0x1fUL
#define TRIGUNIT_REGS_TRIGODELAY_DELAY_SHIFT 0
/* Timestamp TAI seconds of the first VTU output trigger after a start pulse */
#define TRIGUNIT_REGS_TS_FIRSTTRIGTAISEC 0x48UL
/* Timestamp TAI cycles of the first VTU output trigger after a start pulse */
#define TRIGUNIT_REGS_TS_FIRSTTRIGTAICYCLES 0x50UL
/* Timestamp TAI seconds of the last VTU output trigger */
#define TRIGUNIT_REGS_TS_LASTTRIGTAISEC 0x58UL
/* Timestamp TAI cycles of the last VTU output trigger */
#define TRIGUNIT_REGS_TS_LASTTRIGTAICYCLES 0x60UL
/* None */
#define TRIGUNIT_REGS_TRIGDIAG 0x50UL
#define TRIGUNIT_REGS_TRIGDIAG 0x70UL
#define TRIGUNIT_REGS_TRIGDIAG_SIZE 16 /* 0x10 */
struct trigunit_regs {
......@@ -113,14 +125,29 @@ struct trigunit_regs {
/* [0x42]: REG (rw) Delay on the trigger output */
uint16_t trigODelay;
/* padding to: 20 words */
uint32_t __padding_2[3];
/* padding to: 18 words */
uint32_t __padding_2[1];
/* [0x50]: SUBMAP (no description) */
struct vtudiag_regs trigdiag;
/* [0x48]: REG (ro) Timestamp TAI seconds of the first VTU output trigger after a start pulse */
uint64_t TS_FirstTrigTAIsec;
/* [0x50]: REG (ro) Timestamp TAI cycles of the first VTU output trigger after a start pulse */
uint32_t TS_FirstTrigTAIcycles;
/* padding to: 20 words */
uint32_t __padding_3[8];
/* padding to: 22 words */
uint32_t __padding_3[1];
/* [0x58]: REG (ro) Timestamp TAI seconds of the last VTU output trigger */
uint64_t TS_LastTrigTAIsec;
/* [0x60]: REG (ro) Timestamp TAI cycles of the last VTU output trigger */
uint32_t TS_LastTrigTAIcycles;
/* padding to: 28 words */
uint32_t __padding_4[3];
/* [0x70]: SUBMAP (no description) */
struct vtudiag_regs trigdiag;
};
#endif /* __CHEBY__TRIGUNIT_REGS__H__ */
software/include/wr2rf_init_regs.h
View file @ cfa9dbec
#ifndef __CHEBY__WR2RF_INIT_REGS__H__
#define __CHEBY__WR2RF_INIT_REGS__H__
#include "wr2rf_init_rf_regs.h"
#include "hwInfo.h"
#include "wr2rf_init_rf_regs.h"
#include "oc_spi16_regs.h"
#define WR2RF_INIT_REGS_SIZE 16384 /* 0x4000 = 16KB */
......
software/include/wr2rf_rftrigger_regs.h
View file @ cfa9dbec
#ifndef __CHEBY__WR2RF_RFTRIGGER_REGS__H__
#define __CHEBY__WR2RF_RFTRIGGER_REGS__H__
#include "trigunit_regs.h"
#include "vtudiag_regs.h"
#include "trigunit_regs.h"
#define WR2RF_RFTRIGGER_REGS_SIZE 272 /* 0x110 */
/* None */
......
software/include/wr2rf_vme_regs.h
View file @ cfa9dbec
#ifndef __CHEBY__WR2RF_VME_REGS__H__
#define __CHEBY__WR2RF_VME_REGS__H__
#include "wr2rf_ctrl_regs.h"
#include "wr2rf_init_regs.h"
#include "wr2rf_ctrl_regs.h"
#define WR2RF_VME_REGS_SIZE 32768 /* 0x8000 = 32KB */
/* Memory map for the initialization part */
......
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