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wr2rf-vme
Commit 6326222b authored by Tristan Gingold's avatar Tristan Gingold
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vtuCore: more cleanup.

parent e831a704
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Showing with 33 additions and 36 deletions
dependencies/vtu/rtl/vtuCore.vhd
View file @ 6326222b
...@@ -1317,7 +1317,6 @@ begin ...@@ -1317,7 +1317,6 @@ begin
blk_playmem: block blk_playmem: block
is is
signal Mem_AddrZero : std_logic_vector(14 downto 0 );
signal Mem_RdData_prev : std_logic_vector(7 downto 0 ) := (others => '0'); signal Mem_RdData_prev : std_logic_vector(7 downto 0 ) := (others => '0');
signal FirstBit : std_logic_vector(2 downto 0); signal FirstBit : std_logic_vector(2 downto 0);
signal MemAddrIsZeroPrev : std_logic; signal MemAddrIsZeroPrev : std_logic;
...@@ -1362,14 +1361,14 @@ begin ...@@ -1362,14 +1361,14 @@ begin
RunPlayMem => RunPlayMem, RunPlayMem => RunPlayMem,
FirstOutput => FirstOutput, FirstOutput => FirstOutput,
PlayingMem => PlayingMem, PlayingMem => PlayingMem,
LastElem => Mem_LastElem(14 downto 0), LastElem => Mem_LastElem,
RdData => Mem_RdData(7 downto 0), RdData => Mem_RdData,
RdDataPrev => Mem_RdData_prev(7 downto 0), RdDataPrev => Mem_RdData_prev,
RdDataZero => Mem_RdDataZero(7 downto 0), RdDataZero => Mem_RdDataZero,
FirstBit => FirstBit(2 downto 0), FirstBit => FirstBit,
LastBit => Mem_LastBit(2 downto 0), LastBit => Mem_LastBit,
Mem_Addr => Mem_Addr_i(14 downto 0), Mem_Addr => Mem_Addr_i,
DataOut => DataOutPlayMem(7 downto 0)); DataOut => DataOutPlayMem);
StartPlayMem <= Start_i and PlayMemoryMode; StartPlayMem <= Start_i and PlayMemoryMode;
...@@ -1388,26 +1387,24 @@ begin ...@@ -1388,26 +1387,24 @@ begin
process (Clk) process (Clk)
begin begin
if (Clk'event and Clk = '1') then if (Clk'event and Clk = '1') then
PlayingMem_prev <= (PlayingMem); PlayingMem_prev <= PlayingMem;
end if; end if;
end process; end process;
process (Clk) process (Clk)
begin begin
if (Clk'event and Clk = '1') then if (Clk'event and Clk = '1') then
Mem_RdData_prev(7 downto 0) <= (Mem_RdData(7 downto 0)); Mem_RdData_prev <= Mem_RdData;
end if; end if;
end process; end process;
FirstOutput <= PlayingMem and (not PlayingMem_prev); FirstOutput <= PlayingMem and (not PlayingMem_prev);
Mem_Addr(14 downto 0) <= Mem_Addr_i(14 downto 0); Mem_Addr <= Mem_Addr_i;
Mem_AddrZero(14 downto 0) <= (others => '0');
process (Mem_Addr_i , Mem_AddrZero) process (Mem_Addr_i)
begin begin
if Mem_Addr_i(14 downto 0) = Mem_AddrZero(14 downto 0) then if Mem_Addr_i = (14 downto 0 => '0') then
MemAddrIsZero <= '1'; MemAddrIsZero <= '1';
else else
MemAddrIsZero <= '0'; MemAddrIsZero <= '0';
...@@ -1417,15 +1414,17 @@ begin ...@@ -1417,15 +1414,17 @@ begin
process (Clk) process (Clk)
begin begin
if (Clk'event and Clk = '1') then if (Clk'event and Clk = '1') then
MemAddrIsZeroPrev <= (MemAddrIsZero); MemAddrIsZeroPrev <= MemAddrIsZero;
end if; end if;
end process; end process;
ReadDataZero <= MemAddrIsZeroPrev and RunPlayMem;
process (Clk) process (Clk)
begin begin
if (Clk'event and Clk = '1') then if (Clk'event and Clk = '1') then
if (ReadDataZero = '1') then if ReadDataZero = '1' then
Mem_RdDataZero(7 downto 0) <= (Mem_RdData(7 downto 0)); Mem_RdDataZero <= Mem_RdData;
end if; end if;
end if; end if;
end process; end process;
...@@ -1439,8 +1438,6 @@ begin ...@@ -1439,8 +1438,6 @@ begin
"110" when FirstOutput='1' and DataOut_B(6)='1' else "110" when FirstOutput='1' and DataOut_B(6)='1' else
"111" when FirstOutput='1' and DataOut_B(7)='1' else "111" when FirstOutput='1' and DataOut_B(7)='1' else
"000"; "000";
ReadDataZero <= MemAddrIsZeroPrev and RunPlayMem;
end block blk_playmem; end block blk_playmem;
blk_lowfreq: block blk_lowfreq: block
......
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