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wr2rf-vme
Commit 4da46223 authored by Tristan Gingold's avatar Tristan Gingold
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generate 10mhz external clock.

parent 0fb8a3c4
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Showing with 53 additions and 29 deletions
hdl/rtl/wr2rf_sysclks.vhd
View file @ 4da46223
......@@ -39,6 +39,9 @@ entity wr2rf_sysclks is
clk62m5_o : out std_logic;
rst_clk62m5_n_o : out std_logic;
-- For ext_clk, shifted to be resynchronized.
clk10m_o : out std_logic;
clk125m_o : out std_logic;
rst_clk125m_n_o : out std_logic;
......@@ -66,7 +69,7 @@ architecture rtl of wr2rf_sysclks is
signal clkout2b_unused : std_logic;
signal clkout3 : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout4 : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
......@@ -95,7 +98,7 @@ begin
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_MULT_F => 16.000, -- 1Ghz
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 16.000,
......@@ -114,6 +117,10 @@ begin
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT3_USE_FINE_PS => FALSE,
CLKOUT4_DIVIDE => 100,
CLKOUT4_PHASE => -135.000,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT4_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 16.000 )
port map ( -- Output clocks
CLKFBOUT => clkfbout,
......@@ -126,7 +133,7 @@ begin
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT4 => clkout4,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
......@@ -181,6 +188,11 @@ begin
I => clkout3,
O => clks(3) );
clk10m_buf : BUFG
port map (
I => clkout4,
O => clk10m_o );
locked_o <= locked;
arst <= '1' when locked = '0' else '0';
......
hdl/top/wr2rf_vme.vhd
View file @ 4da46223
......@@ -119,6 +119,7 @@ entity wr2rf_vme is
sfp2_led_active_o : out std_logic;
sfp2_led_link_o : out std_logic;
sfp2_rate_select_o : out std_logic;
-- PPS IN & OUT
pps_i : in std_logic;
......@@ -160,12 +161,14 @@ entity wr2rf_vme is
rf1_iqdac_data_n_o : out std_logic_vector(15 downto 0);
rf1_iqdac_dci_p_o : out std_logic;
rf1_iqdac_dci_n_o : out std_logic;
rf1_iqdac_reset_o : out std_logic;
-- rf2 iqdac
rf2_iqdac_data_p_o : out std_logic_vector(15 downto 0);
rf2_iqdac_data_n_o : out std_logic_vector(15 downto 0);
rf2_iqdac_dci_p_o : out std_logic;
rf2_iqdac_dci_n_o : out std_logic;
rf2_iqdac_reset_o : out std_logic;
-- rf1 channel
rf1_sync_p_o : inout std_logic;
......@@ -290,7 +293,7 @@ architecture rtl of wr2rf_vme is
signal clk_sys_62m5 : std_logic;
signal clk_sys_62m5_in : std_logic;
-- signal clk_ext_62m5 : std_logic;
signal clk_ext_10m : std_logic;
signal clk_ext_10m_in : std_logic;
signal clk_gtx_125m : std_logic;
signal clk_sys_select : std_logic;
......@@ -427,7 +430,7 @@ begin
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE)
IOSTANDARD => "LVDS" )
port map (
O => clk_ext_10m, -- Buffer output
O => clk_ext_10m_in, -- Buffer output
I => clk_ext_10m_p_i, -- Diff_p buffer input
IB => clk_ext_10m_n_i ); -- Diff_n buffer input
......@@ -518,7 +521,7 @@ begin
clk_ref_i => clk_sys_62m5, --clk_125m_ref,
clk_ext_mul_i => '0',
clk_ext_mul_locked_i => '1',
clk_ext_i => clk_ext_10m,
clk_ext_i => clk_ext_10m_in,
pps_ext_i => pps_i,
rst_n_i => rst_sys_n,
dac_hpll_load_p1_o => dac_hpll_load_p1_o,
......@@ -543,9 +546,9 @@ begin
phy_loopen_o => phy_loopen,
phy_loopen_vec_o => phy_loopen_vec,
phy_tx_prbs_sel_o => phy_prbs_sel,
phy_sfp_tx_fault_i => '0', --sfp0_los_i,
phy_sfp_los_i => '0', --sfp0_los_i,
phy_sfp_tx_disable_o => open, --sfp0_tx,
phy_sfp_tx_fault_i => sfp1_tx_fault_i,
phy_sfp_los_i => sfp1_los_i,
phy_sfp_tx_disable_o => sfp1_tx_disable_o,
led_act_o => sfp1_led_active_o,
led_link_o => sfp1_led_link_o,
scl_o => wr1_scl_out,
......@@ -635,6 +638,9 @@ begin
sfp1_sda_in <= sfp1_sda_b;
sfp1_tx_disable_o <= '0';
sfp1_rate_select_o <= '1';
sfp2_rate_select_o <= '1';
-- One wire: use port 0 ?
wr_onewire_b <= '0' when (owr_en(0) = '1') else 'Z';
......@@ -725,6 +731,8 @@ begin
clk62m5_o => clk62m5, -- could remove ?
rst_clk62m5_n_o => rst_clk62m5_n,
clk10m_o => clk_ext_10m_o,
clk125m_o => clk125m,
rst_clk125m_n_o => rst_clk125m_n,
......@@ -753,6 +761,10 @@ begin
rf2_iqdac_dci_p_o => rf2_iqdac_dci_p_o,
rf2_iqdac_dci_n_o => rf2_iqdac_dci_n_o );
-- FIXME.
rf1_iqdac_reset_o <= '0';
rf2_iqdac_reset_o <= '0';
-- FIXME: generate rf1_sync, rf2_sync
process (clk62m5) is
begin
......
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