vtucore: fix start of lowfreq, rework test.

026b0437 · Tristan Gingold · f00f4d0d · 026b0437 · 026b0437
Commit 026b0437 authored Apr 28, 2020 by Tristan Gingold
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Showing with 103 additions and 89 deletions

vtuCore.vhd dependencies/vtu/rtl/vtuCore.vhd +2 -2

tb_vtu.vhd hdl/testbench/vtu/tb_vtu.vhd +101 -87

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--- a/dependencies/vtu/rtl/vtuCore.vhd
+++ b/dependencies/vtu/rtl/vtuCore.vhd
@@ -1366,7 +1366,7 @@ begin
    --  Toggle when a pulse is detected.
    process (Clk, RstOrStopSeq)
    begin
-      if RstOrStopSeq = '1' then
+      if RstOrStopSeq = '1' or LowFreqGenerationMode = '0' then
        ClkValueSwitch <= '0';
      elsif (Clk'event and Clk = '1') then
        if DataOut_seq /= x"00" then
@@ -1378,7 +1378,7 @@ begin
    -- Fill data with ones or zeros after one when DataOutPulse='1'
    process (DataOut_seq, RstorStopSeq)
    begin
-      if RstOrStopSeq = '1' then
+      if RstOrStopSeq = '1' or LowFreqGenerationMode = '0'  then
        --  Value at rest.
        DataFilled <= "00000000";
      else

--- a/hdl/testbench/vtu/tb_vtu.vhd
+++ b/hdl/testbench/vtu/tb_vtu.vhd
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;

 use work.wishbone_pkg.all;
 use work.trigunit_regs_consts.all;
@@ -205,6 +206,104 @@ begin
          -- assert s (TRIGUNIT_REGS_STATUS_WRONGWVALUE_OFFSET) = '0' severity error;
        end read_status;

+        procedure test_window (bval : natural; hval : natural; wval : natural) 
+        is
+          variable val : std_logic_vector(15 downto 0);
+          variable dly_clk : natural;
+        begin
+          --  Program the vtu
+          --  Delay between start and the first pulse.
+          write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_BVALUEOFFLINE,
+                        std_logic_vector(to_unsigned(bval, 64)));
+          --  Delay between the pulses.
+          write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_HTVALUEOFFLINE,
+                        std_logic_vector(to_unsigned(hval, 64)));
+          --  Number of pulses.
+          write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEOFFLINE,
+                        std_logic_vector(to_unsigned(wval, 64)));
+
+          --  Windowed mode, enable.
+          write16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONFIGOFFLINE, x"0021");
+
+          --  Remove reset.
+          write16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONTROL, x"0000");
+
+          --  Check status.
+          read_status(val);
+          assert val (TRIGUNIT_REGS_STATUS_MISSVALID_OFFSET) = '0' severity error;
+          assert val (TRIGUNIT_REGS_STATUS_MISSREADY_OFFSET) = '0' severity error;
+          assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '1' severity error;
+          assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '0' severity error;
+          --  Set to one after reset.
+          assert val (TRIGUNIT_REGS_STATUS_WRONGBVALUE_OFFSET) = '1' severity error;
+          assert val (TRIGUNIT_REGS_STATUS_WRONGHTVALUE_OFFSET) = '1' severity error;
+          assert val (TRIGUNIT_REGS_STATUS_WRONGWVALUE_OFFSET) = '1' severity error;
+
+          --  Check online config is 0.
+          read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONFIGONLINE, val);
+          report "config online = " & to_string(val);
+          assert val = x"0000" severity error;
+
+          --  Expect 64 syncs.
+          observer_cmd <= (count => wval, infinite => False, square => False);
+
+          --  Start pulse.
+          start_pulse;
+
+          --  Check status.
+          read_status(val);
+          assert val (TRIGUNIT_REGS_STATUS_MISSVALID_OFFSET) = '0' severity error;
+          assert val (TRIGUNIT_REGS_STATUS_MISSREADY_OFFSET) = '0' severity error;
+          --  Should be 0 if close enough to the start pulse.
+          assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '0' severity error;
+          assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '0' severity error;
+          assert val (TRIGUNIT_REGS_STATUS_WRONGBVALUE_OFFSET) = '0' severity error;
+          assert val (TRIGUNIT_REGS_STATUS_WRONGHTVALUE_OFFSET) = '0' severity error;
+          assert val (TRIGUNIT_REGS_STATUS_WRONGWVALUE_OFFSET) = '0' severity error;
+
+          --  Sync pulse.
+          sync_pulse;
+
+          --  Check ...
+          read_status(val);
+          assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '1' severity error;
+          assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '1' severity error;
+
+          --  Check online config.
+          read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONFIGONLINE, val);
+          report "config online = " & to_string(val);
+          assert val = x"0020" severity error;
+
+          --  Check online registers
+          read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 6, val);
+          assert val = std_logic_vector(to_unsigned(wval, 16)) severity error;
+          read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 4, val);
+          assert val = x"0000" severity error;
+          read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 2, val);
+          assert val = x"0000" severity error;
+          read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 0, val);
+          assert val = x"0000" severity error;
+          read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_HTVALUEONLINE + 6, val);
+          assert val = std_logic_vector(to_unsigned(hval, 16)) severity error;
+          read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_BVALUEONLINE + 6, val);
+          assert val = std_logic_vector(to_unsigned(bval, 16)) severity error;
+
+          --  Wait until end of generation.
+          wait on observer_state;
+          --  Check observer status.
+          assert observer_state = OBS_DONE severity error;
+          dly_clk := (observer_delay + 4999 ps) / 5 ns;
+          assert dly_clk = (8 + bval + 8 + 8)
+            report "window test: bad delay:" & natural'image(dly_clk)
+            severity error;
+          report time'image(observer_delay);
+          assert observer_period = hval * 5 ns;
+          --  Check VTU status.
+          read_status(val);
+          assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '1' severity error;
+          assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '0' severity error;
+        end test_window;
+
        variable val : std_logic_vector(15 downto 0);
    begin
        sync <= '0';
@@ -215,91 +314,7 @@ begin
        --  Program the diag (500us)
        write16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_TRIGDIAG + ADDR_VTUDIAG_REGS_CONTROL, x"0000");

-        --  Program the vtu
-        --  Delay between start and the first pulse.
-        write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_BVALUEOFFLINE, x"0000_0000_0000_0020");
-        --  Delay between the pulses.
-        write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_HTVALUEOFFLINE, x"0000_0000_0000_0008");
-        --  Number of pulses.
-        write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEOFFLINE, x"0000_0000_0000_0040");
-
-        --  Windowed mode, enable.
-        write16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONFIGOFFLINE, x"0021");
-
-        --  Remove reset.
-        write16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONTROL, x"0000");
-
-        --  Check status.
-        read_status(val);
-        assert val (TRIGUNIT_REGS_STATUS_MISSVALID_OFFSET) = '0' severity error;
-        assert val (TRIGUNIT_REGS_STATUS_MISSREADY_OFFSET) = '0' severity error;
-        assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '1' severity error;
-        assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '0' severity error;
-        --  Set to one after reset.
-        assert val (TRIGUNIT_REGS_STATUS_WRONGBVALUE_OFFSET) = '1' severity error;
-        assert val (TRIGUNIT_REGS_STATUS_WRONGHTVALUE_OFFSET) = '1' severity error;
-        assert val (TRIGUNIT_REGS_STATUS_WRONGWVALUE_OFFSET) = '1' severity error;
-
-        --  Check online config is 0.
-        read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONFIGONLINE, val);
-        report "config online = " & to_string(val);
-        assert val = x"0000" severity error;
-
-        --  Expect 64 syncs.
-        observer_cmd <= (count => 64, infinite => False, square => False);
-
-        --  Start pulse.
-        start_pulse;
-
-        --  Check status.
-        read_status(val);
-        assert val (TRIGUNIT_REGS_STATUS_MISSVALID_OFFSET) = '0' severity error;
-        assert val (TRIGUNIT_REGS_STATUS_MISSREADY_OFFSET) = '0' severity error;
-        --  Should be 0 if close enough to the start pulse.
-        assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '0' severity error;
-        assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '0' severity error;
-        assert val (TRIGUNIT_REGS_STATUS_WRONGBVALUE_OFFSET) = '0' severity error;
-        assert val (TRIGUNIT_REGS_STATUS_WRONGHTVALUE_OFFSET) = '0' severity error;
-        assert val (TRIGUNIT_REGS_STATUS_WRONGWVALUE_OFFSET) = '0' severity error;
-
-        --  Sync pulse.
-        sync_pulse;
-
-        --  Check ...
-        read_status(val);
-        assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '1' severity error;
-        assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '1' severity error;
-
-        --  Check online config.
-        read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONFIGONLINE, val);
-        report "config online = " & to_string(val);
-        assert val = x"0020" severity error;
-
-        --  Check online registers
-        read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 6, val);
-        assert val = x"0040" severity error;
-        read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 4, val);
-        assert val = x"0000" severity error;
-        read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 2, val);
-        assert val = x"0000" severity error;
-        read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 0, val);
-        assert val = x"0000" severity error;
-        read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_HTVALUEONLINE + 6, val);
-        assert val = x"0008" severity error;
-        read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_BVALUEONLINE + 6, val);
-        assert val = x"0020" severity error;
-
-        --  Wait until end of generation.
-        wait on observer_state;
-        --  Check observer status.
-        assert observer_state = OBS_DONE severity error;
-        report natural'image(observer_delay / 5 ns);
-        report time'image(observer_delay);
-        assert observer_period = 8 * 5 ns;
-        --  Check VTU status.
-        read_status(val);
-        assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '1' severity error;
-        assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '0' severity error;
+        test_window (25, 13, 7);

        -------------------------------------------------------------------------------------------------

@@ -325,10 +340,9 @@ begin
        --  Lowfreq generation, enable.
        write16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONFIGOFFLINE, x"0041");

-        --  Expect 64 syncs.
        observer_cmd <= (count => 20, infinite => true, square => true);

-        report "test 3 - start";
+        report "test 3 - start - lowFreq";
        start_pulse;

        read_status(val);