... | @@ -8,3 +8,155 @@ Metastability can enter the system because the White Rabbit clocked nco_reset si |
... | @@ -8,3 +8,155 @@ Metastability can enter the system because the White Rabbit clocked nco_reset si |
|
The process and methodology is described in the following document.
|
|
The process and methodology is described in the following document.
|
|
|
|
|
|
[wr2rf_timing_calibration.pdf](uploads/76eec09e829f27a0acfb78ec77587ffd/wr2rf_timing_calibration.pdf)
|
|
[wr2rf_timing_calibration.pdf](uploads/76eec09e829f27a0acfb78ec77587ffd/wr2rf_timing_calibration.pdf)
|
|
|
|
|
|
|
|
Extracted document:
|
|
|
|
|
|
|
|
# Configuring timing delays for WR2RF
|
|
|
|
|
|
|
|
Before commencing to calibrate timing delays for a WR2RF card it is important that the card has
|
|
|
|
reached thermal equilibrium in its installation. The card has an oven controlled oscillator and this
|
|
|
|
takes approximately 5 minutes to reach operating conditions. It's recommended to start calibration
|
|
|
|
after 15 minutes.
|
|
|
|
|
|
|
|
# Configuring timing delays for the DDS
|
|
|
|
|
|
|
|
The picture below depicts the connections between the DDS and FPGA that are important to
|
|
|
|
consider for timing calibration.
|
|
|
|
|
|
|
|
The signal IOUpdate resets the phase accumulators on the DDS AD9910. Internally, this signal is
|
|
|
|
sampled by a clock called SYNC_CLK which is divided by 4 version of the SYS_CLK frequency.
|
|
|
|
The SYS_CLK is derived from the incoming 1 GHz reference clock from the PLL. We have to
|
|
|
|
ensure that IOUpdate is cleanly sampled by the SYNC_CLK. The FPGA provides a fine delay
|
|
|
|
circuit to adjust the output timing of the IOUpdate signal, implemented using OSERDES and
|
|
|
|
ODELAY cells.
|
|
|
|
|
|
|
|
To achieve this we must provide a stream of NCO resets which in turn will trigger an IOUpdate. We
|
|
|
|
then increase the delay of IOUpdate until we observe the DDS output jump onto the next
|
|
|
|
SYNC_CLK sampling edge. The SYNC_CLK has a 4 ns period, so the DDS output will phase will
|
|
|
|
be reset 4 ns later. We have to observe this phase reset, and observe it slip by two SYNC_CLK
|
|
|
|
periods and then place the delay for IOUpdate between these values.
|
|
|
|
|
|
|
|
To observe and make these measurement, configure an oscilloscope to trigger off the nco_reset
|
|
|
|
signal and observe the RF out signal (configured to be the DDS signal). The place of measurement
|
|
|
|
is usually around 120 – 130 ns after nco_reset.
|
|
|
|
|
|
|
|
# Configuring timing delays for the trigger units in an RF channel on WR2RF
|
|
|
|
|
|
|
|
For each RF channel on a WR2RF card, there are three places where metastability can be
|
|
|
|
introduced into the system and observed on the two trigger unit outputs, located on the front panel.
|
|
|
|
This may be due to incorrect timings and delays having been set, or are the default when initialising
|
|
|
|
the card.
|
|
|
|
|
|
|
|
The aim of this section is to define a procedure that allows calibration of these delays so they may
|
|
|
|
be avoided. The following functional overview highlights the different clock domains and their
|
|
|
|
interfaces. Blue, denotes a WR clock domain, red denotes RF clocks and signals and orange/yellow
|
|
|
|
indicate the VTU clock, a divided (by 8) version of the RF clock.
|
|
|
|
|
|
|
|
Where can metastability be introduced into the system?
|
|
|
|
|
|
|
|
* The phase of the RFNCO is reset within the WR clock domain. This signal must be
|
|
|
|
synchronised into the RF clock domain via the first trigger unit. However, there is a fixed
|
|
|
|
phase relationship for any given RF frequency.
|
|
|
|
|
|
|
|
* Trigger unit 1 drives its output off the FPGA and into an external jitter cleaning flip-flop.
|
|
|
|
This T1 signal must avoid the set-up and hold window of this flip-flop.
|
|
|
|
|
|
|
|
* Trigger unit 2 drives its output off the FPGA and into an external jitter cleaning flip-flop.
|
|
|
|
This T2 signal must avoid the set-up and hold window of this flip-flop. The path between T1
|
|
|
|
and T2 is fully timed by the FPGA.
|
|
|
|
|
|
|
|
# Stable RF
|
|
|
|
|
|
|
|
There are two stages to the process:
|
|
|
|
|
|
|
|
The first is to consider that the RF signal produced by the RFNCO, nonIQMod and WR2RF PCB is
|
|
|
|
not stable until 950 ns after nco_reset has occurred. This is a minimum value.
|
|
|
|
|
|
|
|
For a fuller description of this issue please refer to this page:
|
|
|
|
https://ohwr.org/project/wr2rf-vme/wikis/wr2rf-operational-timings
|
|
|
|
|
|
|
|
To avoid this issue, there is a coarse delay (cdelay) block, provided within the WR clock domain to
|
|
|
|
delay sync signal into the first trigger unit. It provides up to 2 us of delay. It is followed by a fine
|
|
|
|
delay circuit that can delay the signal by an additional 16 ns, in 1 ns steps. In experiments with
|
|
|
|
proton injection frequencies, 75 clock cycles or 1.2 us has provided stable results.
|
|
|
|
|
|
|
|
# Method – Requirements
|
|
|
|
|
|
|
|
To follow steps 1 to 4 it is necessary that the card is receiving an RF train that provides regular
|
|
|
|
nco_resets.
|
|
|
|
|
|
|
|
## Method – Step 1 – coarse delay
|
|
|
|
|
|
|
|
To be sure we are clear of any RF instabilities, inspect the RF output signal whilst triggering on a
|
|
|
|
delayed version of the nco_reset. This signal (cdelay applied only) can be observed via a front panel
|
|
|
|
lemo:
|
|
|
|
|
|
|
|
```
|
|
|
|
./wr2rf -s $slot lemo-dbg-sel tmgio3 nco_reset_delayed
|
|
|
|
```
|
|
|
|
|
|
|
|
Try setting the coarse delay value to 75 cycles via this command:
|
|
|
|
```
|
|
|
|
./wr2rf -s $slot nco-reset-delay 1 75 0
|
|
|
|
```
|
|
|
|
|
|
|
|
If the delayed version of nco_reset is clear of the RF stabilities we can proceed to configure the fine
|
|
|
|
delay.
|
|
|
|
|
|
|
|
## Methods – Steps 2, 3 and 4 - overview
|
|
|
|
|
|
|
|
We plan to increase the programmable delays in each of the three places where metastability can
|
|
|
|
occur, such that our signal is being sampled on the following clock edge. At this point, our output
|
|
|
|
will appear 1 clock cycle later. Measuring the skew between the nco_reset and either T1 or T2 will
|
|
|
|
allow us to determine if the output has been sampled on a later clock edge. The delay at which the
|
|
|
|
sampling change occurs, is the worst choice. We need to be half a clock period away from this
|
|
|
|
delay.
|
|
|
|
|
|
|
|
For steps 2-4, route the signal nco_reset to the front panel:
|
|
|
|
```
|
|
|
|
./wr2rf -s $slot lemo-dbg-sel tmgio3 nco_reset
|
|
|
|
```
|
|
|
|
|
|
|
|
## Method – Step 2 – fine delay
|
|
|
|
|
|
|
|
Observe the skew between nco_reset and the T1 trigger unit output. Sweep across the full range of
|
|
|
|
fine delay values 0 through to 15. This should be sufficient to observe two or three changes in the
|
|
|
|
RF clocks sampling points. Choose a fine delay value mid-way between these sampling changes.
|
|
|
|
```
|
|
|
|
./wr2rf -s $slot nco-reset-delay 1 75 [0-15]
|
|
|
|
```
|
|
|
|
|
|
|
|
## Method – Step 3 – T1 flip-flop
|
|
|
|
|
|
|
|
Observe the skew between nco_reset and the T1 trigger unit output. Changing the programmable
|
|
|
|
delay on the trigger unit output from the FPGA has two elements:
|
|
|
|
|
|
|
|
* An ODELAY cell that provides changes in delay of 78 ps, up to 31 x 78 ps
|
|
|
|
|
|
|
|
* A half-cycle delay
|
|
|
|
|
|
|
|
Combined together, the half-cycle delay and ODELAY should provide close to 5 ns of total delay, if
|
|
|
|
the incoming RF clock has a 200 MHz frequency.
|
|
|
|
|
|
|
|
Binary chop through this delay space until the RF sampling point changes. A sequence may look
|
|
|
|
something like this for trigger unit 1 on RF channel 1:
|
|
|
|
|
|
|
|
```
|
|
|
|
./wr2rf -s $slot vtu 1.1 vtu-iodelay half_cycle_delay odelay_value
|
|
|
|
./wr2rf -s $slot vtu 1.1 vtu-iodelay 0 0x0
|
|
|
|
./wr2rf -s $slot vtu 1.1 vtu-iodelay 1 0x1f
|
|
|
|
./wr2rf -s $slot vtu 1.1 vtu-iodelay 1 0x0
|
|
|
|
./wr2rf -s $slot vtu 1.1 vtu-iodelay 1 0x10
|
|
|
|
```
|
|
|
|
|
|
|
|
and so on, depending on where the RF sampling point changes.
|
|
|
|
|
|
|
|
There is a small chance that the metastability region cannot be found. In this event, set the delay to
|
|
|
|
midpoint of the search, e.g.
|
|
|
|
```
|
|
|
|
./wr2rf -s $slot vtu 1.1 vtu-iodelay 0 0x1f
|
|
|
|
```
|
|
|
|
|
|
|
|
## Method – Step 4 – T2 flip-flop
|
|
|
|
As per Step 3 and the T1 flip-flop, but now we should observe the skew between nco_reset and the
|
|
|
|
T2 output. |
|
|
|
\ No newline at end of file |