WR Switch Versions
Version Compatibility for the WR Switch
It can be difficult to understand how versioning work as the WR switch
is separated in 3 different parts: hw, hdl, sw.
Below you can see the table that summaries wich version can be used with
wich software.
Notes: the correct gateware version is already included in the software
version
Hardware version | Software version | Gateware (HDL) version |
v3.0 (prototype) | No supported | No supported |
v3.1 (prototype) | No supported | No supported |
v3.2 |
|
wrs3-gw.tar.gz |
v3.2 | v3.1* | wrs3-gw.tar.gz |
v3.2 | v3.3.1* (v3.3 has an issue with FAN) | wrs3.3-gw.tar.gz (wr-switch-hdl:commit:240657df) |
v3.3-L (LX130T FPGA) | v3.3*, v3.3.1 | wrs3.3-gw.tar.gz (wr-switch-hdl:commit:240657df) |
v3.3-H (LX240T FPGA) | v4.1*, v4.0, v3.3, v3.3.1 | wrs4.0-gw.tar.gz |
v3.4-H (LX240T FPGA) | v4.1* | wrs4.0-gw.tar.gz |
*: recommended version
Changes in software:
Please check the roadmap for software releases
Changes in gateware:
Please check the roadmap for gateware releases
Changes in hardware:
Changes for v3.4
Please check the v3.4 release notes
Changes for v3.3
Schematics:**
Connector_GTX.SchDoc:
- P/N of the J1 changed to QTS-048-02-L-LD-DP (8 mm height stack-up)
- Pin-90 signal connected to FAN_BOX_EN
- Pin-92 signal connected to FAN_PSU_EN
I2C_Multiplexers.SchDoc:
- Removed I2C Temperature Sensor TMP100 IC7 for sensing PCB Tª (placed close the PSU)
TEST_USB.SchDoc:
- Removed the two 1:2 multiplexer controlled by the FPGA.
- Used two independent USB CP2101 chips and connectors for ARM and FPGA.
- Resistors for pull-up and pull-down changed from 3K3 to 4K7.
- Connectors_GPIOs.SchDoc:
- Cases of the DB9 and USB connectors tied to chassis.
- P/N of the J2 changed to QTS-048-02-L-LD-DP (8 mm height stack-up)
- Removed FAN_FPGA controller
- FAN_BOX_EN and FAN_PSU_EN controlled by the FPGA in order to allow easy PWM implementation.
- Added capacitors for filtering PWM output signals.
- Removed tachometers fan signals.
- Added general function push-button.
- Added PMOS to allow switch on-off the +12V of the fans.
- Fan's connectors changed by P/N 61900211121of Würth (2 pins THT)
Main.SchDoc:
- Removed Chassis connections
- Added the I2C_Peripherals sheet:
- Added I2C GPIO controller
- Added push-button to select the ARM booting
- Added a bi-colour red/green led for ARM error communication
- Added a bi-colour red/green led for PSU OK/error
- Added 4bit dip-switch to indicate the PCB version
- Added the TMP100 I2C IC7 Tª sensor removed from I2C_Multiplexers.
PCB:**
- PCB shape changed
- RS232 and USB Test connectors moved to the back panel of the switch.
- SFP cases moved about 2,4mm inside PCB
- USB connectors moved to the PCB edge
- Stack-up changed to 6 layers.
- Gigabit signals moved to internal routing layers to reduce the emitted radiations (CE Label test requirement)
Changes for v3.2
Schematics:**
Connector_GTX.SchDoc:
- Added signals ARM_DEBUG_TXD, ARM_DEBUG_RXD (both from ARM) and USB_SWITCH_CTR (from FPGA)
- Powe_Supply.SchDoc:
- R37 changed from 4K7 to 10K
- C39 and C40 voltage rated increased up to 10V
I2C_Multiplexers.SchDoc:
- Added I2C Temperature Sensor TMP100 for sensing PCB Tª (placed close the PSU)
- FPGA_USB.SchDoc name changed by TEST_USB.SchDoc:
- Added two 1:2 multiplexer controlled by the FPGA. By default the usb port is connected to the ARM.
- USB CP2101 chip configuration changed to bus powered.
Connectors_GPIOs.SchDoc:
- Added individual PSU fan controlled by the signal FAN_BOX_EN_PB7.
- Added 0R resistors to choice the FPGA fan voltage (5V or 12V).
WR_LINK.SchDoc:
- Serial resistor on leds changed by 49R9 (FPGA fed) and by 133R (I2C fed)
PCB:**
- Power supply connector J7 orientation changed in order to allow connection of the new PSU.
- Added teardrops on vias.
Changes for v3.1
SCB_PLLs:
- R61 changed to o.c. The V3 works with 62,5MHz DMTD clock instead of the foreseen 125MHz).
- C188 not mounted by defect.
- AD9516 resistor changed to 100/330R in signals SDIO, SDO, LD and STATUS
Power Supply:
- R234 changed from 10K to 9K31 to increase +2V5 up to 2V6
CPU_JTAG_Power_PLL:
- R3 and R5 values swapped (ARM BMS pin).
- Pull-up R10 changed from JRTCK to JTCK
Connectors:
- USB connector CON1 not used.
- CN2 connector (for uTCA clocks) not used.
FPGA_Configuration:
- Q2 changed by a PMOSFET. Footprint error fixed.
CPU_EBI1_FPGA_Memory:
- SPI Flash changed from AT45DB642 to AT45DB321 (Atmel bug). Footprint changed to keep compatibility of two components.
- SPI Flash divisor on SO signal changed to 100/300R
- Added jumper to select/deselect boot memories. Added a GPIO jumper too (Alessandro requirement).
CPU_IO_Ports:
- Resistor for current limiting of LEDs changed to 330R to increase luminosity.
SMI_Link_7-12:
- Removed FPGA free global clock to J3 connector.
FPGA_System_Monitor:
- FPGA global clock connected to CLK10MHZ_EXT signal clock.
FPGA_Peripherals_Control:
- PLL_STAT signal connected to MRCC FPGA pin clock.
- FPGA_RS232_RXD divider changed to 100/330R
SCB_CLKs:
- IC11 and R38 power supply changed to +2V5
RS232_and_USB:
- RS232 R1out divider changed to 100/330R
Compatibility between SCB, miniBP & Box.
When we are talking about the HW of the WR switch we are talking about the full equipment that includes:
- SCB board (The main board with the ARM and FPGA)
- miniBP 18p (The backplane board with 18 SFP)
- Box (The Box for 18p version)
Below you will find a list of which element is compatible between them self in case you want to upgrade the SCB but keep the other parts of your equipment. This table should be only used on an indicative basis. Be aware that Seven Solutions will reject the warranty if the box has been opened.
SCB HW ver | miniBP HW ver | Box HW ver |
v3.4 | v3.3 | v3.4 |
v3.3 | v3.3 | v3.3 |
v3.2 | v3.3 | v3.3 |
v3.3 | v3.2 | v3.2 |
v3.2 | v3.2 | v3.2 |
v3.1 | v3.1 | v3.1 |
v3.1 | v3.0 | v3.1 |
v3.1 | v3.0 | v3.0 |
--
3 March 2015