... | @@ -89,106 +89,11 @@ notes](https://www.ohwr.org/project/wr-switch-hw/wikis/Release-v33) |
... | @@ -89,106 +89,11 @@ notes](https://www.ohwr.org/project/wr-switch-hw/wikis/Release-v33) |
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Please check the v3.2 [release
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Please check the v3.2 [release
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notes](https://www.ohwr.org/project/wr-switch-hw/wikis/Release-v32)
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notes](https://www.ohwr.org/project/wr-switch-hw/wikis/Release-v32)
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*Schematics:***
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Connector\_GTX.SchDoc:
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- Added signals ARM\_DEBUG\_TXD, ARM\_DEBUG\_RXD (both from ARM) and
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USB\_SWITCH\_CTR (from FPGA)
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- Powe\_Supply.SchDoc:
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- R37 changed from 4K7 to 10K
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- C39 and C40 voltage rated increased up to 10V
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I2C\_Multiplexers.SchDoc:
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- Added I2C Temperature Sensor TMP100 for sensing PCB Tª (placed close
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the PSU)
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- FPGA\_USB.SchDoc name changed by TEST\_USB.SchDoc:
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- Added two 1:2 multiplexer controlled by the FPGA. By default the usb
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port is connected to the ARM.
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- USB CP2101 chip configuration changed to bus powered.
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Connectors\_GPIOs.SchDoc:
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- Added individual PSU fan controlled by the signal FAN\_BOX\_EN\_PB7.
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- Added 0R resistors to choice the FPGA fan voltage (5V or 12V).
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WR\_LINK.SchDoc:
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- Serial resistor on leds changed by 49R9 (FPGA fed) and by 133R (I2C
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fed)
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*PCB:***
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- Power supply connector J7 orientation changed in order to allow
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connection of the new PSU.
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- Added teardrops on vias.
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### Changes for v3.1
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### Changes for v3.1
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Please check the v3.1 [release
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Please check the v3.1 [release
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notes](https://www.ohwr.org/project/wr-switch-hw/wikis/Release-v31)
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notes](https://www.ohwr.org/project/wr-switch-hw/wikis/Release-v31)
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SCB\_PLLs:
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- R61 changed to o.c. The V3 works with 62,5MHz DMTD clock instead of
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the foreseen 125MHz).
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- C188 not mounted by defect.
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- AD9516 resistor changed to 100/330R in signals SDIO, SDO, LD and
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STATUS
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Power Supply:
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- R234 changed from 10K to 9K31 to increase +2V5 up to 2V6
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CPU\_JTAG\_Power\_PLL:
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- R3 and R5 values swapped (ARM BMS pin).
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- Pull-up R10 changed from JRTCK to JTCK
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Connectors:
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- USB connector CON1 not used.
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- CN2 connector (for uTCA clocks) not used.
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FPGA\_Configuration:
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- Q2 changed by a PMOSFET. Footprint error fixed.
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CPU\_EBI1\_FPGA\_Memory:
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- SPI Flash changed from AT45DB642 to AT45DB321 (Atmel bug). Footprint
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changed to keep compatibility of two components.
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- SPI Flash divisor on SO signal changed to 100/300R
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- Added jumper to select/deselect boot memories. Added a GPIO jumper
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too (Alessandro requirement).
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CPU\_IO\_Ports:
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- Resistor for current limiting of LEDs changed to 330R to increase
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luminosity.
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SMI\_Link\_7-12:
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- Removed FPGA free global clock to J3 connector.
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FPGA\_System\_Monitor:
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- FPGA global clock connected to CLK10MHZ\_EXT signal clock.
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FPGA\_Peripherals\_Control:
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- PLL\_STAT signal connected to MRCC FPGA pin clock.
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- FPGA\_RS232\_RXD divider changed to 100/330R
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SCB\_CLKs:
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- IC11 and R38 power supply changed to +2V5
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RS232\_and\_USB:
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- RS232 R1out divider changed to 100/330R
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-----
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-----
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## Compatibility between SCB, miniBP & Box.
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## Compatibility between SCB, miniBP & Box.
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... | | ... | |