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# WRS versions
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# WR Switch Versions
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# Versions of WR Switch
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## Version Compatibility for the WR Switch
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It can be difficult to understand how versioning work as the WR switch
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is separated in 3 different parts: hw, hdl, sw.
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... | ... | @@ -56,6 +56,29 @@ version* |
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*\*: recommended version*
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## Changes in software:
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### Changes for v3.3 (soon available)
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- Correct RTU aging bug
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- Improve booting procedure (LEDs & Fans)
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- Add gateware version to shw\_ver tool
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- Mount RO to prevent CRC error in NAND flash
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### Changes for v3.3-rc1 (a.k.a v3.2)
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- Add support for both LX130T & LX240T FPGA
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- Add shw\_ver tool to check versions
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- Add backward compatibility for IO pins
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- Improve PWM using FPGA core
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- Improve non-DHCP configuration
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### Changes for v3.1
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- Correct booting script to correct CRC error while flashing NAND
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- Introduce two MACs address during flashing
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- Improve building procedure (barebox, md5 check, ...)
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## Changes in gateware:
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Please check the roadmap in the
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... | ... | @@ -65,117 +88,156 @@ Please check the roadmap in the |
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### Changes for v3.3
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Schematics:
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#### Schematics:
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Connector\_GTX.SchDoc:
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P/N of the J1 changed to QTS-048-02-L-LD-DP (8 mm height stack-up)
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Pin-90 signal connected to FAN\_BOX\_EN
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Pin-92 signal connected to FAN\_PSU\_EN
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Powe\_Supply.SchDoc:
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N/A
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- P/N of the J1 changed to QTS-048-02-L-LD-DP (8 mm height stack-up)
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- Pin-90 signal connected to FAN\_BOX\_EN
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- Pin-92 signal connected to FAN\_PSU\_EN
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I2C\_Multiplexers.SchDoc:
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Removed I2C Temperature Sensor TMP100 IC7 for sensing PCB Tª (placed
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- Removed I2C Temperature Sensor TMP100 IC7 for sensing PCB Tª (placed
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close the PSU)
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TEST\_USB.SchDoc:
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Removed the two 1:2 multiplexer controlled by the FPGA.
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Used two independent USB CP2101 chips and connectors for ARM and FPGA.
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Resistors for pull-up and pull-down changed from 3K3 to 4K7.
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Connectors\_GPIOs.SchDoc:
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Cases of the DB9 and USB connectors tied to chassis.
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P/N of the J2 changed to QTS-048-02-L-LD-DP (8 mm height stack-up)
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Removed FAN\_FPGA controller
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FAN\_BOX\_EN and FAN\_PSU\_EN controlled by the FPGA in order to allow
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easy PWM implementation.
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Added capacitors for filtering PWM output signals.
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Removed tachometers fan signals.
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Added general function push-button.
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Added PMOS to allow switch on-off the +12V of the fans.
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Fan's connectors changed by P/N 61900211121of Würth (2 pins THT)
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WR\_LINK.SchDoc:
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N/A
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- Removed the two 1:2 multiplexer controlled by the FPGA.
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- Used two independent USB CP2101 chips and connectors for ARM and
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FPGA.
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- Resistors for pull-up and pull-down changed from 3K3 to 4K7.
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- Connectors\_GPIOs.SchDoc:
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- Cases of the DB9 and USB connectors tied to chassis.
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- P/N of the J2 changed to QTS-048-02-L-LD-DP (8 mm height stack-up)
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- Removed FAN\_FPGA controller
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- FAN\_BOX\_EN and FAN\_PSU\_EN controlled by the FPGA in order to
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allow easy PWM implementation.
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- Added capacitors for filtering PWM output signals.
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- Removed tachometers fan signals.
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- Added general function push-button.
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- Added PMOS to allow switch on-off the +12V of the fans.
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- Fan's connectors changed by P/N 61900211121of Würth (2 pins THT)
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Main.SchDoc:
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Removed Chassis connections
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Added the I2C\_Peripherals sheet:
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Added I2C GPIO controller
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Added push-button to select the ARM booting
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Added a bi-colour red/green led for ARM error communication
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Added a bi-colour red/green led for PSU OK/error
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Added 4bit dip-switch to indicate the PCB version
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Added the TMP100 I2C IC7 Tª sensor removed from I2C\_Multiplexers.
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PCB:
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PCB shape changed
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RS232 and USB Test connectors moved to the back panel of the switch.
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SFP cases moved about 2,4mm inside PCB
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USB connectors moved to the PCB edge
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Stack-up changed to 6 layers.
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Gigabit signals moved to internal routing layers to reduce the emitted
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radiations (CE Label test requirement)
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- Removed Chassis connections
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- Added the I2C\_Peripherals sheet:
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- Added I2C GPIO controller
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- Added push-button to select the ARM booting
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- Added a bi-colour red/green led for ARM error communication
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- Added a bi-colour red/green led for PSU OK/error
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- Added 4bit dip-switch to indicate the PCB version
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- Added the TMP100 I2C IC7 Tª sensor removed from I2C\_Multiplexers.
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#### PCB:
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...
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- PCB shape changed
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- RS232 and USB Test connectors moved to the back panel of the switch.
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- SFP cases moved about 2,4mm inside PCB
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- USB connectors moved to the PCB edge
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- Stack-up changed to 6 layers.
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- Gigabit signals moved to internal routing layers to reduce the
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emitted radiations (CE Label test requirement)
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### Changes for v3.2
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Schematics:
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#### Schematics:
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Connector\_GTX.SchDoc:
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Added signals ARM\_DEBUG\_TXD, ARM\_DEBUG\_RXD (both from ARM) and
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- Added signals ARM\_DEBUG\_TXD, ARM\_DEBUG\_RXD (both from ARM) and
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USB\_SWITCH\_CTR (from FPGA)
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Powe\_Supply.SchDoc:
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R37 changed from 4K7 to 10K
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C39 and C40 voltage rated increased up to 10V
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- Powe\_Supply.SchDoc:
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- R37 changed from 4K7 to 10K
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- C39 and C40 voltage rated increased up to 10V
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I2C\_Multiplexers.SchDoc:
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Added I2C Temperature Sensor TMP100 for sensing PCB Tª (placed close the
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PSU)
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FPGA\_USB.SchDoc name changed by TEST\_USB.SchDoc:
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Added two 1:2 multiplexer controlled by the FPGA. By default the usb
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- Added I2C Temperature Sensor TMP100 for sensing PCB Tª (placed close
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the PSU)
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- FPGA\_USB.SchDoc name changed by TEST\_USB.SchDoc:
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- Added two 1:2 multiplexer controlled by the FPGA. By default the usb
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port is connected to the ARM.
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USB CP2101 chip configuration changed to bus powered.
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- USB CP2101 chip configuration changed to bus powered.
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Connectors\_GPIOs.SchDoc:
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Added individual PSU fan controlled by the signal FAN\_BOX\_EN\_PB7.
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Added 0R resistors to choice the FPGA fan voltage (5V or 12V).
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- Added individual PSU fan controlled by the signal FAN\_BOX\_EN\_PB7.
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- Added 0R resistors to choice the FPGA fan voltage (5V or 12V).
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WR\_LINK.SchDoc:
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Serial resistor on leds changed by 49R9 (FPGA fed) and by 133R (I2C fed)
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PCB:
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Power supply connector J7 orientation changed in order to allow
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- Serial resistor on leds changed by 49R9 (FPGA fed) and by 133R (I2C
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fed)
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#### PCB:
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- Power supply connector J7 orientation changed in order to allow
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connection of the new PSU.
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Added teardrops on vias.
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- Added teardrops on vias.
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### Changes for v3.1
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1.- SCB\_PLLs:
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R61 changed to o.c. The V3 works with 62,5MHz DMTD clock instead of the
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foreseen 125MHz).
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C188 not mounted by defect.
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AD9516 resistor changed to 100/330R in signals SDIO, SDO, LD and STATUS
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2.- Power Supply:
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R234 changed from 10K to 9K31 to increase +2V5 up to 2V6
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3.- CPU\_JTAG\_Power\_PLL:
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R3 and R5 values swapped (ARM BMS pin).
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Pull-up R10 changed from JRTCK to JTCK
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4.- Connectors:
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USB connector CON1 not used.
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CN2 connector (for uTCA clocks) not used.
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5.- FPGA\_Configuration:
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Q2 changed by a PMOSFET. Footprint error fixed.
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6.- CPU\_EBI1\_FPGA\_Memory:
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SPI Flash changed from AT45DB642 to AT45DB321 (Atmel bug). Footprint
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SCB\_PLLs:
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- R61 changed to o.c. The V3 works with 62,5MHz DMTD clock instead of
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the foreseen 125MHz).
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- C188 not mounted by defect.
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- AD9516 resistor changed to 100/330R in signals SDIO, SDO, LD and
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STATUS
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Power Supply:
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- R234 changed from 10K to 9K31 to increase +2V5 up to 2V6
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CPU\_JTAG\_Power\_PLL:
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- R3 and R5 values swapped (ARM BMS pin).
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- Pull-up R10 changed from JRTCK to JTCK
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Connectors:
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- USB connector CON1 not used.
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- CN2 connector (for uTCA clocks) not used.
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FPGA\_Configuration:
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- Q2 changed by a PMOSFET. Footprint error fixed.
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CPU\_EBI1\_FPGA\_Memory:
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- SPI Flash changed from AT45DB642 to AT45DB321 (Atmel bug). Footprint
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changed to keep compatibility of two components.
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SPI Flash divisor on SO signal changed to 100/300R
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Added jumper to select/deselect boot memories. Added a GPIO jumper too
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(Alessandro requirement).
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7.- CPU\_IO\_Ports:
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Resistor for current limiting of LEDs changed to 330R to increase
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- SPI Flash divisor on SO signal changed to 100/300R
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- Added jumper to select/deselect boot memories. Added a GPIO jumper
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too (Alessandro requirement).
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CPU\_IO\_Ports:
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- Resistor for current limiting of LEDs changed to 330R to increase
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luminosity.
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8.- SMI\_Link\_7-12:
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Removed FPGA free global clock to J3 connector.
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9.- FPGA\_System\_Monitor:
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FPGA global clock connected to CLK10MHZ\_EXT signal clock.
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10.- FPGA\_Peripherals\_Control:
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PLL\_STAT signal connected to MRCC FPGA pin clock.
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FPGA\_RS232\_RXD divider changed to 100/330R
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11.- SCB\_CLKs:
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IC11 and R38 power supply changed to +2V5
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12.- RS232\_and\_USB:
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RS232 R1out divider changed to 100/330R
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SMI\_Link\_7-12:
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- Removed FPGA free global clock to J3 connector.
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FPGA\_System\_Monitor:
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- FPGA global clock connected to CLK10MHZ\_EXT signal clock.
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FPGA\_Peripherals\_Control:
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- PLL\_STAT signal connected to MRCC FPGA pin clock.
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- FPGA\_RS232\_RXD divider changed to 100/330R
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SCB\_CLKs:
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- IC11 and R38 power supply changed to +2V5
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RS232\_and\_USB:
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- RS232 R1out divider changed to 100/330R
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