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|| **POWERING**| Comments | Done|
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|1|**Redesign** P085, IC32, to be at least 30A|Use WREN-like powering| |
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|2| No need for **ferrite beads** on the DC/DC outputs| Maybe leave for initial debugging||
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|2| No need for **ferrite beads** on the DC/DC outputs; maybe leave for initial debugging| Relevant comment from [previous review](https://ohwr.org/project/wr-switch-hw-v4/uploads/85cd8b73d6d139b8f40ee1378e8e3110/WRSv4-MainBoard_Schematics_Review-3-PeterJ_and_GuidoV-2021-12.pdf): *Add a small ferrite in the +12V0 line to VDD (A7, A8) See also ZL9010M datasheet Figure 19*||
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|3| A lot of missing **power vias** near decoupling capacitors|||
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|4|Use **standard coils**: L74, L76, L75, L77 CMC windings are connected in parallel. That won't work. CMCs are very fragile to current imbalance. To make them work, use common ferrite core or multi-windong CMCs||
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|5|Use **VCCINT below FPGA as the DC/DC feedback**||
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... | ... | @@ -12,8 +12,8 @@ |
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|| **TO CHECK**| Comments| Done|
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|1| **TR2**: check input stage, assume GM clock as input |https://ohwr.org/project/wr-switch-hw-v4/issues/44||
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|2| **IC49**: what's the purpose| Check also D22 rating||
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|1| **TR2**: check input stage, assume GM clock as input |Relevant comment from [previous review](https://ohwr.org/project/wr-switch-hw-v4/uploads/85cd8b73d6d139b8f40ee1378e8e3110/WRSv4-MainBoard_Schematics_Review-3-PeterJ_and_GuidoV-2021-12.pdf): Sheet 3: “GM_CLOCKING.SchDoc” and https://ohwr.org/project/wr-switch-hw-v4/issues/44||
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|2| **IC49 LTC4358**: what's the purpose? Check also D22 rating| Relevant comment from [previous review](https://ohwr.org/project/wr-switch-hw-v4/uploads/85cd8b73d6d139b8f40ee1378e8e3110/WRSv4-MainBoard_Schematics_Review-3-PeterJ_and_GuidoV-2021-12.pdf): *Consider to connect VDD pin of LTC4358 via a 100 ohm resistor a 100nF capacitor (“VDD Hold-Up Circuit” see figure 2b of LTC4358 datasheet)*||
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-----------------------------------------------------------------------
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... | ... | @@ -25,7 +25,7 @@ |
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|4| **PS_MIOS**: check how's Linux driver support for I2C mux (IC20). Maybe for some of the stuff that needs to be frequently accessed (e.g. OLED?) would make sense to connect to PL and use PL-instantiated IIC ipcore| | |
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|5|**USB_interfaces**: with proper EEPROM configuration, you can use FTDI chip not only for UART, but also as JTAG for the FPGA|Greg to provide DI/OT fw |
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|6|**ESD7016MUTAG**: leave the footprint| Check if pin 11, remote sense should be connected (ATX standard/PSU - remote sense on pin 11, useful if we do not have enough copper on power planes) |
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|7|**TVS** for FMC status lines instead of PESD3V3L1BA|https://ohwr.org/project/wr-switch-hw-v4/issues/44||
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|7|**TVS** for FMC status lines instead of PESD3V3L1BA| Relevant comments from [previous review](https://ohwr.org/project/wr-switch-hw-v4/uploads/85cd8b73d6d139b8f40ee1378e8e3110/WRSv4-MainBoard_Schematics_Review-3-PeterJ_and_GuidoV-2021-12.pdf): *ESD protection on J15 signals? They are directly connected to the FPGA pins. Max voltage on pin is: HP VCCO =1V8 + 0.3 See Table 7; not sure how to interpret overshoot? For example ESD122DMYR might not be sufficient.* And https://ohwr.org/project/wr-switch-hw-v4/issues/44||
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|8|**USBC** requires [5k1 pulldown resistors on CC lines](https://www.allaboutcircuits.com/technical-articles/introduction-to-usb-type-c-which-pins-power-delivery-data-transfer/) to work as USB device
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|9| **SFP I2C** interface is not protected with TVS while the MGT IFC is|||
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|10|Connect **D5, D6 pin 5 to 3V3**|It would lower the clamping voltage||
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... | ... | |