... | @@ -18,7 +18,19 @@ Please attach a txt or add your comments directly |
... | @@ -18,7 +18,19 @@ Please attach a txt or add your comments directly |
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- GregK
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- GregK
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SCH
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**/!\ Power planes**
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- [Report of VCCINT PDN analysis at 10A]([DC_2023-05-26_23.50.zip](uploads/db5df118a2f511d0760007952a7bd992/DC_2023-05-26_23.50.zip)); it should actually be at 30A for such a big SoC
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- P3V3, P0V85 power supplies underrated: P3V3 to be at least 8..10A. P0V85 to be at least 30A.
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- Proposes steps:
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* Good power budget with necessary margins; I use Excel sheets and ADI online tool
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* Re-design of power supplies
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* SI analysis of all 10G links using Hyperlynx and eye diagrams/BERR and PCB update
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* SI analysis of the SDRAM using SI-DDR and PCB update
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* PDN analysis for every rail. I did it for two rails and found critical issues so far
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* PCB fixes – it’s necessary to add more polygons for VCCINT and 3.3V rails
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**SCH**
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- some designators are rotated (I know, there is an option in settings)
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- some designators are rotated (I know, there is an option in settings)
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- enable PN view of ICs, like ESD7016MUTAG
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- enable PN view of ICs, like ESD7016MUTAG
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- are you sure ESD7016MUTAG would work here? It's clamping voltage is far too high to protect the FPGA bank
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- are you sure ESD7016MUTAG would work here? It's clamping voltage is far too high to protect the FPGA bank
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... | @@ -38,7 +50,7 @@ SCH |
... | @@ -38,7 +50,7 @@ SCH |
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https://www.allaboutcircuits.com/technical-articles/introduction-to-usb-type-c-which-pins-power-delivery-data-transfer/
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https://www.allaboutcircuits.com/technical-articles/introduction-to-usb-type-c-which-pins-power-delivery-data-transfer/
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- why SATA? PCIe SSDs are much faster, the M2 keying is different. I miss annotation about M2 keying
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- why SATA? PCIe SSDs are much faster, the M2 keying is different. I miss annotation about M2 keying
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PCB
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**PCB**
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- missing return vias for MGT signals (critical) and all differential signals
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- missing return vias for MGT signals (critical) and all differential signals
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- MGT vias below FPGA seem to be not impedance matched - there is random polygon pour and NFPs are not removed. Was there SI simulation performed? I'd like to see the eye diagram for 10G
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- MGT vias below FPGA seem to be not impedance matched - there is random polygon pour and NFPs are not removed. Was there SI simulation performed? I'd like to see the eye diagram for 10G
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- random GND pour around SDRAM traces breakes impedance. Did you run SI-DDR simulation? It doesn't look so
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- random GND pour around SDRAM traces breakes impedance. Did you run SI-DDR simulation? It doesn't look so
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