... | @@ -16,19 +16,19 @@ Please attach a txt or add your comments directly |
... | @@ -16,19 +16,19 @@ Please attach a txt or add your comments directly |
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**Schematics:**
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**Schematics:**
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- power_supply: would be good to add a graph with intended power sequencing - just for clarity
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- [TODO] power_supply: would be good to add a graph with intended power sequencing - just for clarity
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- PS_MIOS: check how's Linux driver support for I2C mux (IC20). Maybe for some of the stuff that needs to be frequently accessed (e.g. OLED?) would make sense to connect to PL and use PL-instantiated IIC ipcore?
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- [TODO] PS_MIOS: check how's Linux driver support for I2C mux (IC20). Maybe for some of the stuff that needs to be frequently accessed (e.g. OLED?) would make sense to connect to PL and use PL-instantiated IIC ipcore?
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- USB_interfaces: with proper EEPROM configuration, you can use FTDI chip not only for UART, but also as JTAG for the FPGA. We have it sorted out in DI/OT. Then, when working with Vivado you don't need any special JTAG cable, just a regular USB cable connected to your FTDI. This requires also connecting a configuration EEPROM to pins EECS, EECLK, EEDATA
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- [TODO] USB_interfaces: with proper EEPROM configuration, you can use FTDI chip not only for UART, but also as JTAG for the FPGA. We have it sorted out in DI/OT. Then, when working with Vivado you don't need any special JTAG cable, just a regular USB cable connected to your FTDI. This requires also connecting a configuration EEPROM to pins EECS, EECLK, EEDATA
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**Layout:**
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**Layout:**
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- I don't think routing SD card or eMMC lines requires backdrilled vias.
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- [to be seen] I don't think routing SD card or eMMC lines requires backdrilled vias.
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- Some traces are not routed, e.g. SATA_RX_P/N or SD_CTRL.SD_D0/2
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- [TODO] Some traces are not routed, e.g. SATA_RX_P/N or SD_CTRL.SD_D0/2
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- Add GND vias for return current close to high speed signals, or even better, spread uniformly GND vias on PCB to connect well GND layers together and to ensure return paths for high speed signals.
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- [TODO] Add GND vias for return current close to high speed signals, or even better, spread uniformly GND vias on PCB to connect well GND layers together and to ensure return paths for high speed signals.
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- [X:165mm, Y: 150mm] in L2 there is thick (2mm) P3V8 trace that connects to other layers through very tiny vias (0.3mm hole size). Increase vias dimension.
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- [TODO][X:165mm, Y: 150mm] in L2 there is thick (2mm) P3V8 trace that connects to other layers through very tiny vias (0.3mm hole size). Increase vias dimension.
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- DEM adds teardrops in all designs recently, but it was not done for this PCB.
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- [done at the end] DEM adds teardrops in all designs recently, but it was not done for this PCB.
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- missing licensing and URL in the silkscreen
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- [done at the end] missing licensing and URL in the silkscreen
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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... | @@ -39,9 +39,9 @@ Please attach a txt or add your comments directly |
... | @@ -39,9 +39,9 @@ Please attach a txt or add your comments directly |
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**/!\ Power planes**
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**/!\ Power planes**
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- [Report of VCCINT PDN analysis at 10A](uploads/78b06d86d2c0e018ef1e03e503fd06bc/DC_2023-05-26_23.50.zip) shows failures
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- [Report of VCCINT PDN analysis at 10A](uploads/78b06d86d2c0e018ef1e03e503fd06bc/DC_2023-05-26_23.50.zip) shows failures
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- ideally the analysis should be done at 30A for such a big SoC
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- ideally the analysis should be done at 30A for such a big SoC
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- P3V3, P0V85 power supplies underrated
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- [TODO] P3V3, P0V85 power supplies underrated
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- P3V3 to be at least 8..10A
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- [should be ok] P3V3 to be at least 8..10A
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- P0V85 to be at least 30A.
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- [TODO, IC32 is the problem, WREN-like power supply, unify] P0V85 to be at least 30A.
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- Proposed next steps:
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- Proposed next steps:
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* Good power budget with necessary margins; I use Excel sheets and ADI online tool
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* Good power budget with necessary margins; I use Excel sheets and ADI online tool
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* Re-design of power supplies
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* Re-design of power supplies
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... | @@ -49,26 +49,29 @@ Please attach a txt or add your comments directly |
... | @@ -49,26 +49,29 @@ Please attach a txt or add your comments directly |
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* SI analysis of the SDRAM using SI-DDR and PCB update
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* SI analysis of the SDRAM using SI-DDR and PCB update
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* PDN analysis for every rail. I did it for two rails and found critical issues so far
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* PDN analysis for every rail. I did it for two rails and found critical issues so far
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* PCB fixes – it’s necessary to add more polygons for VCCINT and 3.3V rails
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* PCB fixes – it’s necessary to add more polygons for VCCINT and 3.3V rails
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NOTE: ATX standard/PSU - remote sense on pin 11, useful if we do not have enough copper on power planes
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**SCH**
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**SCH**
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- some designators are rotated (I know, there is an option in settings)
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- some designators are rotated (I know, there is an option in settings)
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- enable PN view of ICs, like ESD7016MUTAG
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- enable PN view of ICs, like ESD7016MUTAG
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- are you sure ESD7016MUTAG would work here? It's clamping voltage is far too high to protect the FPGA bank
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- [leave the footprint] are you sure ESD7016MUTAG would work here? It's clamping voltage is far too high to protect the FPGA bank
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- I'd use unipolar TVS for FMC status lines instead of PESD3V3L1BA
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- [TODO for expansion conne] I'd use unipolar TVS for FMC status lines instead of PESD3V3L1BA
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- LMX2594RHAT is hard to get
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- [leave for the time being, we have the component] LMX2594RHAT is hard to get
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- we have TR2, Tr3, TR4, don't we want to use galvanic isolation (ground loop removal)
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- [leave as is, works fine for RF] we have TR2, Tr3, TR4, don't we want to use galvanic isolation (ground loop removal)
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- I miss annotation about power level at P5 input
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- [it is 10MHz input, TODO + check the input stage and TR2] I miss annotation about power level at P5 input
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- L74, L76, L75, L77 CMC windings are connected in parallel. That won't work. CMCs are very fragile to current impalance. To make them work, use common ferrite core or multi-windong CMCs
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- [TODO: use standard coils] L74, L76, L75, L77 CMC windings are connected in parallel. That won't work. CMCs are very fragile to current impalance. To make them work, use common ferrite core or multi-windong CMCs
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- what's the purpose of IC49? Are we going to connect any other PSU?
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- [to be checked, D22-to low voltage rating] what's the purpose of IC49? Are we going to connect any other PSU?
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- please add annotation about fan PN, I cannot verify the connector wiring
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NOTE: behavior of PSU might depend on design, check
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- add series 4k7 protection resistor in series with FANx_PRESENT input, We don't want FPGA damage when somebody inserts fan with different wiring
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- [TODO: change fan connectors] please add annotation about fan PN, I cannot verify the connector wiring
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- I'd connect D26 pin 5 to 3V3 and add series PWM input resistors. We don't want fan controller damage when somebody inserts fan with different wiring
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- [TODO] add series 4k7 protection resistor in series with FANx_PRESENT input, We don't want FPGA damage when somebody inserts fan with different wiring
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- isn the voltage rail nomenclature correct? P3AV3 looks weird, don't we use P3V3A in all OHWR designs?
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- [TODO] I'd connect D26 pin 5 to 3V3 and add series PWM input resistors. We don't want fan controller damage when somebody inserts fan with different wiring
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- SFP I2C interface is not protected with TVS while the MGT IFC is.
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- [TODO] isn the voltage rail nomenclature correct? P3AV3 looks weird, don't we use P3V3A in all OHWR designs?
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- connect D5, D6 pin 5 to 3V3. It would lower the clamping voltage
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- [to be checked] SFP I2C interface is not protected with TVS while the MGT IFC is.
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- USBC requires 5k1 pulldown resistors on CC lines to work as USB device
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- [TODO] connect D5, D6 pin 5 to 3V3. It would lower the clamping voltage
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- [TODO] USBC requires 5k1 pulldown resistors on CC lines to work as USB device
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https://www.allaboutcircuits.com/technical-articles/introduction-to-usb-type-c-which-pins-power-delivery-data-transfer/
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https://www.allaboutcircuits.com/technical-articles/introduction-to-usb-type-c-which-pins-power-delivery-data-transfer/
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- why SATA? PCIe SSDs are much faster, the M2 keying is different. I miss annotation about M2 keying
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- [SATA is ok, keying to be checked] why SATA? PCIe SSDs are much faster, the M2 keying is different. I miss annotation about M2 keying
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**PCB**
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**PCB**
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- missing return vias for MGT signals (critical) and all differential signals
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- missing return vias for MGT signals (critical) and all differential signals
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... | @@ -78,14 +81,14 @@ https://www.allaboutcircuits.com/technical-articles/introduction-to-usb-type-c-w |
... | @@ -78,14 +81,14 @@ https://www.allaboutcircuits.com/technical-articles/introduction-to-usb-type-c-w |
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- several accute corners on negative layers, especially polygons under FPGA
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- several accute corners on negative layers, especially polygons under FPGA
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- no defined polygon pour sequence, anyway, GND polygon should not cover other polygons! This may lead to serious issues during re-pouring of all polygons
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- no defined polygon pour sequence, anyway, GND polygon should not cover other polygons! This may lead to serious issues during re-pouring of all polygons
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- no PDN analysis were performed. Otherwise one would discover that single piece of polygon cannot supply the core of such big FPGAs. I usually have to use 3 polygons in parallel to distribute VCCINT
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- no PDN analysis were performed. Otherwise one would discover that single piece of polygon cannot supply the core of such big FPGAs. I usually have to use 3 polygons in parallel to distribute VCCINT
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- no thermal bridges for SMD pads on top layer. This makes solering challenging. No reason to do this way for all pads.
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- [Have thermal on all SMD pads] no thermal bridges for SMD pads on top layer. This makes solering challenging. No reason to do this way for all pads.
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- are you sure 0V85 consumes less than 12A? I used much stronger DC/DC converters for much smaller chips
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- [to be changed] are you sure 0V85 consumes less than 12A? I used much stronger DC/DC converters for much smaller chips
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- why not to use VCCINT below FPGA as the DC/DC feedback?
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- [check ! good idea] why not to use VCCINT below FPGA as the DC/DC feedback?
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- 3 vias that connect L51 to power plane is just a joke :D They will burn a few moments after power on.
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- [TODO] 3 vias that connect L51 to power plane is just a joke :D They will burn a few moments after power on.
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- a lot of acute copper on top layer and other layers - it will affect reliability
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- [acute angles -> to be fixed] a lot of acute copper on top layer and other layers - it will affect reliability
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- ferrite beads before and after DC/DC do not make much sense. Their impedance for such low frequency is mostly pure resistance. They only cause DC drop. They makes sense only during initial debugging.
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- [leave for initial debugging] ferrite beads before and after DC/DC do not make much sense. Their impedance for such low frequency is mostly pure resistance. They only cause DC drop. They makes sense only during initial debugging.
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- DDR4_DQS8_x routed over split polygon
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- [TODO] DDR4_DQS8_x routed over split polygon
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- what is this strange unconnected trace around clocking ? whhy not use keepout lines?
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- [it is guard-ring, should be connected to vias, a debugging feature, leave as is] what is this strange unconnected trace around clocking ? whhy not use keepout lines?
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- those beefy CMCs don't make any sense - they won't perform any function
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- those beefy CMCs don't make any sense - they won't perform any function
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- ZL9101M is EOL
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- ZL9101M is EOL
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- SI and PDN analysis at this stage does not make much sense.
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- SI and PDN analysis at this stage does not make much sense.
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