... | ... | @@ -13,6 +13,22 @@ Please attach a txt or add your comments directly |
|
|
|
|
|
- GregD
|
|
|
|
|
|
**Schematics:**
|
|
|
|
|
|
- power_supply: would be good to add a graph with intended power sequencing - just for clarity
|
|
|
- PS_MIOS: check how's Linux driver support for I2C mux (IC20). Maybe for some of the stuff that needs to be frequently accessed (e.g. OLED?) would make sense to connect to PL and use PL-instantiated IIC ipcore?
|
|
|
- USB_interfaces: with proper EEPROM configuration, you can use FTDI chip not only for UART, but also as JTAG for the FPGA. We have it sorted out in DI/OT. Then, when working with Vivado you don't need any special JTAG cable, just a regular USB cable connected to your FTDI. This requires also connecting a configuration EEPROM to pins EECS, EECLK, EEDATA
|
|
|
|
|
|
|
|
|
**Layout:**
|
|
|
|
|
|
- I don't think routing SD card or eMMC lines requires backdrilled vias.
|
|
|
- Some traces are not routed, e.g. SATA_RX_P/N or SD_CTRL.SD_D0/2
|
|
|
- Add GND vias for return current close to high speed signals, or even better, spread uniformly GND vias on PCB to connect well GND layers together and to ensure return paths for high speed signals.
|
|
|
- [X:165mm, Y: 150mm] in L2 there is thick (2mm) P3V8 trace that connects to other layers through very tiny vias (0.3mm hole size). Increase vias dimension.
|
|
|
- DEM adds teardrops in all designs recently, but it was not done for this PCB.
|
|
|
- missing licensing and URL in the silkscreen
|
|
|
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
|
|
... | ... | |