... | @@ -8,11 +8,9 @@ Please ignore few non-critical issues like DRCs (mostly silkscreen related) and |
... | @@ -8,11 +8,9 @@ Please ignore few non-critical issues like DRCs (mostly silkscreen related) and |
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
-------------------------------------------------------------------------------
|
|
|
|
|
|
**Comments**
|
|
*Please attach a txt or add your comments directly*
|
|
|
|
|
|
Please attach a txt or add your comments directly
|
|
### GregD
|
|
|
|
|
|
- GregD
|
|
|
|
|
|
|
|
**Schematics:**
|
|
**Schematics:**
|
|
|
|
|
... | @@ -33,7 +31,7 @@ Please attach a txt or add your comments directly |
... | @@ -33,7 +31,7 @@ Please attach a txt or add your comments directly |
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
-------------------------------------------------------------------------------
|
|
|
|
|
|
- GregK
|
|
### GregK
|
|
|
|
|
|
|
|
|
|
**/!\ Power planes**
|
|
**/!\ Power planes**
|
... | @@ -99,7 +97,7 @@ https://www.allaboutcircuits.com/technical-articles/introduction-to-usb-type-c-w |
... | @@ -99,7 +97,7 @@ https://www.allaboutcircuits.com/technical-articles/introduction-to-usb-type-c-w |
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
-------------------------------------------------------------------------------
|
|
|
|
|
|
- Maciej
|
|
### Maciej
|
|
|
|
|
|
Some Clarifications:
|
|
Some Clarifications:
|
|
- Reg GregK's "why SATA? PCIe SSDs are much faster", relevant issues where M.2 choice was discussed: #23, #39
|
|
- Reg GregK's "why SATA? PCIe SSDs are much faster", relevant issues where M.2 choice was discussed: #23, #39
|
... | @@ -116,9 +114,15 @@ Feedback/review; |
... | @@ -116,9 +114,15 @@ Feedback/review; |
|
- License note missing and WR logo of bad quality ;-)
|
|
- License note missing and WR logo of bad quality ;-)
|
|
-------------------------------------------------------------------------------
|
|
-------------------------------------------------------------------------------
|
|
|
|
|
|
- Paul
|
|
### Paul
|
|
|
|
- Quiescent current for vccint is already 2.5A. Any power consumption estimate from vivado with a preliminary gateware?
|
|
|
|
On spexi7u I use the DC/DC from Infineon with 30A output current capability on vccint. To be considered to update the design with a similar solution.
|
|
|
|
- IMHO, no need for ferrite beads on the DC/DC outputs
|
|
|
|
- A lot of missing power vias near decoupling capacitors
|
|
|
|
- Is it allowed to put via in pads for decoupling capacitors located under the fpga?
|
|
|
|
- Tracks for decoupling capacitors are often too small, I’m used to set the track width equal to the diameter of the vias
|
|
|
|
- Design checklist XTP427 from Xilinx is missing
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
-------------------------------------------------------------------------------
|
|
|
|
|
|
- Tom
|
|
|
|
|
|
|