... | @@ -17,7 +17,7 @@ Please attach a txt or add your comments directly |
... | @@ -17,7 +17,7 @@ Please attach a txt or add your comments directly |
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- GregK
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- GregK
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- SCH
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SCH
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- some designators are rotated (I know, there is an option in settings)
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- some designators are rotated (I know, there is an option in settings)
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- enable PN view of ICs, like ESD7016MUTAG
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- enable PN view of ICs, like ESD7016MUTAG
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- are you sure ESD7016MUTAG would work here? It's clamping voltage is far too high to protect the FPGA bank
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- are you sure ESD7016MUTAG would work here? It's clamping voltage is far too high to protect the FPGA bank
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... | @@ -37,6 +37,26 @@ Please attach a txt or add your comments directly |
... | @@ -37,6 +37,26 @@ Please attach a txt or add your comments directly |
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https://www.allaboutcircuits.com/technical-articles/introduction-to-usb-type-c-which-pins-power-delivery-data-transfer/
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https://www.allaboutcircuits.com/technical-articles/introduction-to-usb-type-c-which-pins-power-delivery-data-transfer/
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- why SATA? PCIe SSDs are much faster, the M2 keying is different. I miss annotation about M2 keying
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- why SATA? PCIe SSDs are much faster, the M2 keying is different. I miss annotation about M2 keying
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PCB
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- missing return vias for MGT signals (critical) and all differential signals
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- MGT vias below FPGA seem to be not impedance matched - there is random polygon pour and NFPs are not removed. Was there SI simulation performed? I'd like to see the eye diagram for 10G
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- random GND pour around SDRAM traces breakes impedance. Did you run SI-DDR simulation? It doesn't look so
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- errors in impedance profiles in stackup editor
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- several accute corners on negative layers, especially polygons under FPGA
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- no defined polygon pour sequence, anyway, GND polygon should not cover other polygons! This may lead to serious issues during re-pouring of all polygons
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- no PDN analysis were performed. Otherwise one would discover that single piece of polygon cannot supply the core of such big FPGAs. I usually have to use 3 polygons in parallel to distribute VCCINT
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- no thermal bridges for SMD pads on top layer. This makes solering challenging. No reason to do this way for all pads.
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- are you sure 0V85 consumes less than 12A? I used much stronger DC/DC converters for much smaller chips
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- why not to use VCCINT below FPGA as the DC/DC feedback?
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- 3 vias that connect L51 to power plane is just a joke :D They will burn a few moments after power on.
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- a lot of acute copper on top layer and other layers - it will affect reliability
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- ferrite beads before and after DC/DC do not make much sense. Their impedance for such low frequency is mostly pure resistance. They only cause DC drop. They makes sense only during initial debugging.
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- DDR4_DQS8_x routed over split polygon
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- what is this strange unconnected trace around clocking ? whhy not use keepout lines?
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- those beefy CMCs don't make any sense - they won't perform any function
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- ZL9101M is EOL
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- the SI
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- Maciej
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- Maciej
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