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## Project description
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## Project description
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This project describes the development of the version 4 of the White
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This project describes the development of the hardware of version 4 of the White
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Rabbit switch.
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Rabbit Switch.
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The White Rabbit Switch is an open hardware design of an **18-ports
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The White Rabbit Switch is an open hardware design of an **Ethernet switch** licensed under [CERN
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Ethernet switch** licensed under [CERN
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OHL 1.2](https://www.ohwr.org/project/cernohl/wiki). It is a central
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OHL 1.2](https://www.ohwr.org/project/cernohl/wiki). It is a central
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element of a White Rabbit network and was designed as a part of the
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element of a White Rabbit network and is designed as a part of the [White Rabbit
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[White Rabbit
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project](https://www.ohwr.org/project/white-rabbit/wiki).
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project](https://www.ohwr.org/project/white-rabbit/wiki).
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The WR Switch can be used with official
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[firmware](https://www.ohwr.org/project/wr-switch-hw/wiki#project-information)
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releases. As the design is open it can also be used as the hardware
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platform for other, non-White Rabbit
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projects.
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*Figure 1: WR Switch v3.4 - v4.0 may look different**
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-----
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-----
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## Main Features
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## Main Features
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*TO BE EDITED is spec of V3.4**
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**Currently, the features are being discussed [here](project/wr-switch-hw-v4/wikis/Features-choice), their final list will be published here when agreed**
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- Front Panel
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- 5 SMC connectors
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- 1-PPS input and output
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- 62.5 MHz output
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- 10 MHz output (software configurable)
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- 10 MHz input
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- 18 cages for Gigabit SFP transceivers (connected to Xilinx GTXs)
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- 10/100 Ethernet management port (connected to ARM CPU)
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- USB-uart management port (connected to ARM CPU)
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- *Power* and *Status* LEDs
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- *Link* and *Act* LEDs for each SFP cage
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<!-- end list -->
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- Back Panel
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- 2x USB-uart debugging port (connected to ARM CPU and FPGA I/O
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pins)
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- power button
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- 2x cooling fan
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- 2x microswitch
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- 1x grounding connector
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<!-- end list -->
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- Xilinx Virtex-6 FPGA (XC6VLX240T)
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- Clocking resources
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- 1x Low-Jitter Clock Generator (TI CDCM61002, used as DMTD offset
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clock in [WR Switch
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HDL](https://www.ohwr.org/project/wr-switch-hdl/wiki))
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- 1x 25MHz VCXO, FRETHE025 controlled by DAC with SPI interface
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(AD5662, used to drive CDCM61002 generator)
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- 1x 25MHz VCO controlled by DAC with SPI interface (AD5662, used
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to drive AD9516 generator)
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- 1x 25MHz XO oscillator FNETHE025 (main FPGA clock)
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- 14-Output Clock Generator with Integrated 1.6 GHz VCO (AD9516,
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clock signals for Xilinx GTXs, uTCA connectors)
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- 1x Internal Oscillator (VM53S3-25.000, tuned to follow WR master
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clock or followed in Free Running mode)
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<!-- end list -->
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- ARM Atmel AT91 SAM9G45 CPU
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- Memory:
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- 64MB DDR2
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- 256MB NAND
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- 8MB boot flash
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<!-- end list -->
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- Others:
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- 1x FPGA JTAG connector
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- 1x ARM JTAG connector
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- 2x I2C multiplexer (PCA9548A)
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- 1x I2C GPIO driver (PCA9554PW, driving *Power* and *Status* LEDs
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on the front panel)
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- 9x I2C GPIO driver (PCA9554PW, driving LEDs for each SFP cage)
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<!-- end list -->
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- Power supply 100-240VAC, 2.0A, 50-60Hz input, 12V DC, 6.66A, 80W
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output
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<!-- end list -->
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- Box dimensions 482.8 x 42.34 x 222 mm
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<!-- end list -->
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- Certification
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- IPC-610 Rev E Class 2
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- ISO-9001
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- ISO-14001
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- CE
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- RoHS
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-----
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-----
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## Project information
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- Production documentation
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- [Firmware](https://www.ohwr.org/project/wr-switch-sw/wiki)
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- [WR Switch
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versions](https://www.ohwr.org/project/wr-switch-sw/wikis/WRS-versions)
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- [Frequently Asked
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Questions](https://www.ohwr.org/project/white-rabbit/wikis/FAQswitch)
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- Gateware for WR Switch
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- Software for WR Switch
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-----
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## Contacts
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## Releases
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- [previous hardware
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### Commercial producers
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releases](https://www.ohwr.org/project/wr-switch-hw/wikis/old-hw-releases)
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-----
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- WRS V4 under design, to be produced by [Seven Solutions](https://sevensols.com/)
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## Contacts
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### Commercial partners involved:
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### Commercial producers
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- [Seven Solutions](https://sevensols.com/)
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- WRS V4 under design, not available
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### General question about project
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### General question about project
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
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- [Maciej Lipinski](mailto:maciej.lipinski@cern.ch) - CERN
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-----
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| ... | @@ -142,10 +43,12 @@ projects. |
... | @@ -142,10 +43,12 @@ projects. |
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|07-03-2014|First ideas of a next generation WRS with one or more 10 Gbps ports|
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|07-03-2014|First ideas of a next generation WRS with one or more 10 Gbps ports|
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|01-07-2016|First collection of requirements for V4 generation switch requested on [wr-dev mailing list](https://lists.ohwr.org/sympa/arc/white-rabbit-dev/2016-07/thrd1.html#00000) (archive)|
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|01-07-2016|First collection of requirements for V4 generation switch requested on [wr-dev mailing list](https://lists.ohwr.org/sympa/arc/white-rabbit-dev/2016-07/thrd1.html#00000) (archive)|
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|07-10-2018|Second collection of requirements for V4 generation switch made on the [10th WR Workshop](https://www.ohwr.org/project/white-rabbit/wikis/oct2018meeting)|
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|07-10-2018|Second collection of requirements for V4 generation switch made on the [10th WR Workshop](https://www.ohwr.org/project/white-rabbit/wikis/oct2018meeting)|
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|30-09-2018 | First "Technical proposal for the design of a new White Rabbit Switch" by [Seven Solutions](https://sevensols.com/)|
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|28-11-2018 | [Seven Solutions](https://sevensols.com/) ordered to conduct preliminary design study and produce Technical <br />Specification with definition of architecture and key components selection)|
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|11-07-2019| Preliminary FPGA/CPU choice: ZU11, final decision will be based on the following study in Aug-Sept: <br /> - evaluation of required resources to know what size/package of the FPGA to choose <br /> - verification of determinism/suitability of the gigabit transceivers (GTH) and noise added by FPGA and its pins.|
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|19-07-2019| Two ZCU106 Xilinx Evaluation Boards ordered |
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Erik van der Bij - 17 October 2018
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