| ... | ... | @@ -20,31 +20,20 @@ project](https://www.ohwr.org/project/white-rabbit/wiki). |
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## Project Roadmap
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|**Complete by**|**Event**|**Who**|
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|2020: end March | Preliminary study of features, components, requirements, FPGA/CPU choice <br /> complete by "In-depth study of WRS-v4/18 features" document | Seven Solutions, Creotech |
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|2020: end May | Proposal of WRS-v4/18 main board architecture <br /> complete by "Proposal of WRS-v4/18 architecture" document | Creotech |
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|2020: end May | Verification of 1Gb and 10Gb transceiver in the chosen FPGA/family | CERN |
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|2020: June | Request for feedback from WR community | WR Community |
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|2020: end July | Update of study/proposal documents | Seven Solutions |
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|2020: end December | PCB and enclosure design <br /> completed by delivery of first prototypes | Seven Solutions |
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|2021: end July | Board Support Package (SW) <br /> Production Test Suite (PTS) | Seven Solutions |
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## Project milestones
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1. **[end of March 2020]** - complete preliminary study of features, components, requirements,
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publish [In-depth study of WRS-v4/18 features](uploads/8df374029c4b2a3cc025a59a72edce55/WRS-v4-hw-study.pdf) by SevenSolutions:
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- [Preliminary study of input from the WR community, CERN IT](https://ohwr.org/project/wr-switch-hw-v4/wikis/Features-choice)
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- [In-depth study of WRS-v4/18 features](uploads/8df374029c4b2a3cc025a59a72edce55/WRS-v4-hw-study.pdf) by SevenSolutions
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- [Analysis of resource utilization for the candidate FPGA choice](uploads/31c7019f3c24cb12ec0f8c79c108af59/WRS-v4-resource-utilization.pdf) by Creotech
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- Verification of 1Gb and 10Gb transceiver in the chosen FPGA/family
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2. **[end of May 2020]** - complete and publish proposal of WRS-v4/18 main board architecture (Seven Sols)
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3. **[June 2020]** - request for comments/feedback from the WR community
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4. **[end of July 2020]**Design/production of HW prototype - 2020
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|**Completion**|**Task**|**Deliverable**|**Status**|
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|---------------|--------|---------------|-------|
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|2020: <br /> end March |Study of features, components,<br /> requirements, FPGA/CPU choice - WP1, WP2 | Docs: "Study of WRS-v4/18 features" and <br /> [Analysis of FPGA resource utilization](uploads/31c7019f3c24cb12ec0f8c79c108af59/WRS-v4-resource-utilization.pdf) | Ongoing |
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|2020:<br /> end May | 1. Proposal of WRS-v4/18 main board architecture - WP3 <br /> 2. Verification of 1Gb and 10Gb transceiver - WP4 | 1. Doc:"Proposal of WRS-v4/18 arch"<br /> 2. Demo/prototype | Ongoing|
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|2020: <br />June | Request for feedback from WR community | |
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|2020: <br />end July | Update of study/proposal documents | Updated documents | |
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|2020: <br />end Dec. | 1. Schematics design - WP5 <br /> 2. PCB layout design (DEM) - WP6 <br /> 3. Enclosure design -WP7 <br /> 4. Proper WR support for GTH - WP8| 1 & 2. Prototypes of PCB <br /> 3. Prototype of enclosure <br /> 4. Release of WR cores| |
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|2021: <br />end July | 1. Production Test Suite (PTS) - WP9 <br /> 2. Board Support Package (SW) - WP10 | 1. Product <br /> 2. Prototype | |
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|2021: <br />end Dec. | 1. Porting of gateware + clocking - WP11 <br /> 2. Port of SW with minimal integration of peripherals - WP11 <br /> 3. Integration of new peripherals - WP12| Fully functional WRS at 1GB | |
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| 2022:<br /> end July| Preparation of first release v1 - WP13 | Release | |
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| 2022:<br /> end Dec | Add support of 10Gb to the WRS (timing, not data)- WP14 | Prototype | |
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| 2023:<br /> end July | Preparation of first release v2- WP15 | Release | |
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5. Port of HDL/SW from WRS-v3/18 to the WRS-v4/18 for 1Gb only - 2021 or later
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6. Upgrade of HDL/SW to 10Gb
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| ... | ... | |
