... | @@ -17,6 +17,15 @@ project](https://www.ohwr.org/project/white-rabbit/wiki). |
... | @@ -17,6 +17,15 @@ project](https://www.ohwr.org/project/white-rabbit/wiki). |
|
|
|
|
|
**Possible design with hot-swappable fans and redundant PSU with basic enclosure**
|
|
**Possible design with hot-swappable fans and redundant PSU with basic enclosure**
|
|
|
|
|
|
|
|
## Project information
|
|
|
|
|
|
|
|
- [Preliminary study of input from the WR community, CERN IT](https://ohwr.org/project/wr-switch-hw-v4/wikis/Features-choice)
|
|
|
|
- [In-depth study of WRS-v4/18 features](uploads/8df374029c4b2a3cc025a59a72edce55/WRS-v4-hw-study.pdf) by SevenSolutions:
|
|
|
|
- [Analysis of resource utilization for the candidate FPGA choice](uploads/31c7019f3c24cb12ec0f8c79c108af59/WRS-v4-resource-utilization.pdf) by Creotech
|
|
|
|
- [Frequently Asked Questions](faq)
|
|
|
|
|
|
|
|
---
|
|
|
|
|
|
-----
|
|
-----
|
|
## Project Roadmap
|
|
## Project Roadmap
|
|
|
|
|
... | @@ -28,24 +37,36 @@ project](https://www.ohwr.org/project/white-rabbit/wiki). |
... | @@ -28,24 +37,36 @@ project](https://www.ohwr.org/project/white-rabbit/wiki). |
|
|2020: <br />end July | Update of study/proposal documents | Updated documents | |
|
|
|2020: <br />end July | Update of study/proposal documents | Updated documents | |
|
|
|2020: <br />end Dec. | 1. Schematics design - WP5 <br /> 2. PCB layout design (DEM) - WP6 <br /> 3. Enclosure design -WP7 <br /> 4. Proper WR support for GTH - WP8| 1 & 2. Prototypes of PCB <br /> 3. Prototype of enclosure <br /> 4. Release of WR cores| |
|
|
|2020: <br />end Dec. | 1. Schematics design - WP5 <br /> 2. PCB layout design (DEM) - WP6 <br /> 3. Enclosure design -WP7 <br /> 4. Proper WR support for GTH - WP8| 1 & 2. Prototypes of PCB <br /> 3. Prototype of enclosure <br /> 4. Release of WR cores| |
|
|
|2021: <br />end July | 1. Production Test Suite (PTS) - WP9 <br /> 2. Board Support Package (SW) - WP10 | 1. Product <br /> 2. Prototype | |
|
|
|2021: <br />end July | 1. Production Test Suite (PTS) - WP9 <br /> 2. Board Support Package (SW) - WP10 | 1. Product <br /> 2. Prototype | |
|
|
|2021: <br />end Dec. | 1. Porting of gateware + clocking - WP11 <br /> 2. Port of SW with minimal integration of peripherals - WP11 <br /> 3. Integration of new peripherals - WP12| Fully functional WRS at 1GB | |
|
|
|2021: <br />end Dec. | 1. Porting of gateware + clocking - WP11 <br /> 2. Port of SW with minimal integration of peripherals - WP12 <br /> 3. Integration of new peripherals - WP13| Fully functional WRS at 1GB | |
|
|
| 2022:<br /> end July| Preparation of first release v1 - WP13 | Release | |
|
|
| 2022:<br /> end July| Preparation of first release v1 - WP14 | Release | |
|
|
| 2022:<br /> end Dec | Add support of 10Gb to the WRS (timing, not data)- WP14 | Prototype | |
|
|
| 2022:<br /> end Dec | Add support of 10Gb to the WRS (timing, not data)- WP15 | Prototype | |
|
|
| 2023:<br /> end July | Preparation of first release v2- WP15 | Release | |
|
|
| 2023:<br /> end July | Preparation of first release v2- WP16 | Release | |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
-----
|
|
-----
|
|
|
|
|
|
## Project information
|
|
## Work Packages
|
|
|
|
|
|
- [In-depth study of WRS-v4/18 features](uploads/8df374029c4b2a3cc025a59a72edce55/WRS-v4-hw-study.pdf) by SevenSolutions:
|
|
|**WP **|**Task**|**Company**|**Status**|
|
|
- [Preliminary study of input from the WR community, CERN IT](https://ohwr.org/project/wr-switch-hw-v4/wikis/Features-choice)
|
|
|-------|--------|-----------|-------|
|
|
- [In-depth study of WRS-v4/18 features](uploads/8df374029c4b2a3cc025a59a72edce55/WRS-v4-hw-study.pdf) by SevenSolutions
|
|
|1| Study of WRS-v4/18 features | Seven Solutions | Ongoing
|
|
- [Analysis of resource utilization for the candidate FPGA choice](uploads/31c7019f3c24cb12ec0f8c79c108af59/WRS-v4-resource-utilization.pdf) by Creotech
|
|
|2| Analysis of FPGA resource utilization | Creotech | Competed |
|
|
- [Frequently Asked Questions](faq)
|
|
|3| Proposal of WRS-v4/18 main board architecture | Seven Solutions | Ongoing |
|
|
|
|
|4| Verification of 1Gb and 10Gb transceiver | CERN | Ongoing |
|
|
|
|
|5| Schematics design | | |
|
|
|
|
|6| PCB layout design (DEM) | CERN | |
|
|
|
|
|7| Enclosure design | | |
|
|
|
|
|8| Proper WR support for GTH | CERN | |
|
|
|
|
|9| Production Test Suite (PTS) | | |
|
|
|
|
|10| Board Support Package (SW) | | |
|
|
|
|
|11| Porting of gateware + clocking | | |
|
|
|
|
|12| Port of SW with minimal integration of peripherals | | |
|
|
|
|
|13| Integration of new peripherals | | |
|
|
|
|
|14| Preparation of first release v1 | CERN | |
|
|
|
|
|15| Add support of 10Gb to the WRS (timing, not data | | |
|
|
|
|
|15| reparation of first release v2 | CERN | |
|
|
|
|
-----
|
|
|
|
|
|
---
|
|
|
|
|
|
|
|
|
|
|
|
## Contacts
|
|
## Contacts
|
... | | ... | |