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| Data ports | Number: 18 <br /> Speed: 1 and/or 10 Gbps | **20 ports if space allows?** |
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| Mgmt ports| 2 Ethernet (SFP cage + simple RJ45) <br /> USB Mini-B | **Add RS232 port as suggested?** |
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| CLK IOs | Type: SMC <br />IN_1: 10 MHz <br />IN_2: 1 PPS <br /> OUT_1: 10 MHz<br /> OUT_2: 1 PPS <br /> OUT_3: 62.5 MHz | **SMA or other instead of SMC, differential, LVDS? [see](uploads/576f996e3ab0f2067d3d615ccad635c1/New_WRS_requirements_from_WR_Community.pdf)**<br />**Add input for calibration/TIC or re-use existing?**|
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| CLK IOs | Type: SMC <br />IN_1: 10 MHz <br />IN_2: 1 PPS <br /> OUT_1: 10 MHz<br /> OUT_2: 1 PPS <br /> OUT_3: 62.5 MHz | **SMA or other instead of SMC, differential, LVDS? [see](uploads/576f996e3ab0f2067d3d615ccad635c1/New_WRS_requirements_from_WR_Community.pdf)**<br />**Add input for calibration/TIC/timescale comparison or re-use existing?**|
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| General LEDs| LED_1: Power <br /> LED_2: Status <br /> LED_3: Aux (localization) | **I've added locatiozation led, as suggested**|
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| Port LEDs | LED_1: Link / WR mode / Calib <br /> LED_2: Synced / Activity | |
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## Back panel
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| Feature | Proposal | **To be discussed (TBD)** or Comment |
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| Power | Power switch <br /> Power plug | It is easier to have it in the back for the case when optional <br />redundant/swappable power supply is implemented
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| Power | Power switch <br /> Power plug | It is easier to have it in the back for the case when optional <br />redundant/swappable power supply is implemented.<br /> **The location was controversial, we could study further**
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| Debugging | USB Mini-B FPGA <br /> USB Mini-B CPU | **Not sure whether CPU output is needed/possible**|
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*NOTE: There is no RS232 port in the back (as compared to the previous version of the WR Switch) - it was not really used*
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