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The main purpose of the Clocking FMC is to test/prototype the clocking circuit proposed in the [WRS-4 main board (Hardware_Architecture)](/project/wr-switch-hw-v4/wikis/uploads/c4fa8bc97eeeb551c736146eae7b8e25/WRS-4_main_board_Hardware_Architecture_-v1.7-2020-06-09.pdf) document, section 3.4 (page 25-28). Additionally, the FMC has an SFP cage and it can be used to enable WR on a host board, such as e.g. AFCZ, or ZCU102/ZCU106 eval board.
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## Reviews
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Figure 5 shows a detailed block diagram of the proposed solution. As can be seen in
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| | Date | Design files | Comments | Status |
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| ------ | ---- | ------ | ------ | ------ |
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| 1 |2020-07 | [pdf](uploads/bafa3fcbd86ebd5de2fa91d144da2822/BRD-FCWR-01_V1_0.pdf) [rar](uploads/90c900bc35779996b8cac789f44ef3c0/BRD-FCWR-01.rar) | | Completed |
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| 2 |2020-09 | | | Ongoing |
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The figure shows a detailed block diagram of the proposed solution. As can be seen in
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this figure, the main PLL is the HMC7044 that has the following features of interest for the
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new WRS-4:
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- Possibility to have a mixed scenario (part of the design working with 62.5 MHz
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