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White Rabbit Switch - Gateware
Commits
d49e5993
Commit
d49e5993
authored
Jun 19, 2019
by
Grzegorz Daniluk
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phy determinism for 18-port version
parent
5eb9d456
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93 deletions
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scb_top_synthesis.ucf
top/scb_18ports/scb_top_synthesis.ucf
+38
-85
scb_top_synthesis.vhd
top/scb_18ports/scb_top_synthesis.vhd
+18
-8
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top/scb_18ports/scb_top_synthesis.ucf
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d49e5993
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@@ -690,54 +690,49 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DM
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2019/06/18
INST "gen_phys_bufr[0].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys_bufr[0].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys_bufr[1].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys_bufr[1].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys_bufr[2].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys_bufr[2].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys_bufr[3].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys_bufr[3].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[4].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[4].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[5].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[5].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[6].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[6].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[7].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[7].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[8].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[8].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[9].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[9].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[10].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[10].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[11].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[11].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[12].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[12].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[13].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[13].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[14].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[14].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[15].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[15].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[16].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[16].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[17].U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[17].U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
TIMESPEC TS_ignore1 = FROM Ignore_DMTD TIG;
TIMESPEC TS_ignore2 = TO Ignore_DMTD TIG;
TIMESPEC TS_ignore3 = FROM Ignore_sync_ffs TIG;
TIMESPEC TS_ignore4 = TO Ignore_sync_ffs TIG;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_0" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_1" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_2" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_3" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_4" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_5" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_6" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_7" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_8" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_9" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_10" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_11" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_12" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_13" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_14" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_15" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_16" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_17" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_18" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_19" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_20" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_21" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
...
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@@ -1067,6 +1062,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DM
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_18" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
...
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@@ -1139,29 +1135,6 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DM
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_0" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_1" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_2" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_3" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_4" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_5" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_6" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_7" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_8" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_9" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_10" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_11" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_12" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_13" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_14" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_15" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_16" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_17" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_18" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_19" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_20" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_21" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
...
...
@@ -1505,26 +1478,6 @@ TIMESPEC TS_ignore42 = FROM "fpga_clk_ref_p_i" TO "clk_sys" 20ns DATAPATHONLY;
TIMESPEC TS_ignore43 = FROM "clk_sys" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY;
TIMESPEC TS_ignore44 = FROM "clk_sys" TO "phy_rx_clocks" 20ns DATAPATHONLY;
TIMESPEC TS_ignore45 = FROM "phy_rx_clocks" TO "clk_sys" 20ns DATAPATHONLY;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/07/16
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#TIMESPEC TS_dmtd_input = FROM "DMTD_div_clks" TO "FFS" 0.5 ns DATAPATHONLY;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2013/11/06
...
...
top/scb_18ports/scb_top_synthesis.vhd
View file @
d49e5993
...
...
@@ -716,25 +716,30 @@ begin
--generate first 4 GTXes with BUFR to reduce the number of global clocks
gen_phys_bufr
:
for
i
in
0
to
3
generate
U_PHY
:
wr_gtx_phy_virtex6
U_PHY
:
entity
work
.
wr_gtx_phy_virtex6_lp
generic
map
(
g_simulation
=>
f_bool2int
(
g_simulation
),
g_use_slave_tx_clock
=>
f_bool2int
(
i
/=
(
i
/
4
)
*
4
),
g_use_bufr
=>
true
)
g_use_bufr
=>
true
,
g_id
=>
i
)
port
map
(
clk_gtx_i
=>
clk_gtx
(
i
),
clk_ref_i
=>
clk_ref
,
clk_gtx_i
=>
clk_gtx
(
i
),
clk_ref_i
=>
clk_ref
,
clk_dmtd_i
=>
clk_dmtd
,
tx_data_i
=>
to_phys
(
i
)
.
tx_data
,
tx_k_i
=>
to_phys
(
i
)
.
tx_k
,
tx_disparity_o
=>
from_phys
(
i
)
.
tx_disparity
,
tx_enc_err_o
=>
from_phys
(
i
)
.
tx_enc_err
,
rx_rbclk_o
=>
from_phys
(
i
)
.
rx_clk
,
rx_rbclk_sampled_o
=>
from_phys
(
i
)
.
rx_sampled_clk
,
rx_data_o
=>
from_phys
(
i
)
.
rx_data
,
rx_k_o
=>
from_phys
(
i
)
.
rx_k
,
rx_enc_err_o
=>
from_phys
(
i
)
.
rx_enc_err
,
rx_bitslide_o
=>
from_phys
(
i
)
.
rx_bitslide
,
rst_i
=>
to_phys
(
i
)
.
rst
,
debug_o
=>
from_phys
(
i
)
.
debug
,
debug_i
=>
to_phys
(
i
)
.
debug
,
loopen_i
=>
to_phys
(
i
)
.
loopen
,
pad_txn_o
=>
gtx_txn_o
(
i
),
pad_txp_o
=>
gtx_txp_o
(
i
),
...
...
@@ -747,25 +752,30 @@ begin
gen_phys
:
for
i
in
4
to
c_NUM_PHYS
-1
generate
U_PHY
:
wr_gtx_phy_virtex6
U_PHY
:
entity
work
.
wr_gtx_phy_virtex6_lp
generic
map
(
g_simulation
=>
f_bool2int
(
g_simulation
),
g_use_slave_tx_clock
=>
f_bool2int
(
i
/=
(
i
/
4
)
*
4
),
g_use_bufr
=>
false
)
g_use_bufr
=>
false
,
g_id
=>
i
)
port
map
(
clk_gtx_i
=>
clk_gtx
(
i
),
clk_ref_i
=>
clk_ref
,
clk_gtx_i
=>
clk_gtx
(
i
),
clk_ref_i
=>
clk_ref
,
clk_dmtd_i
=>
clk_dmtd
,
tx_data_i
=>
to_phys
(
i
)
.
tx_data
,
tx_k_i
=>
to_phys
(
i
)
.
tx_k
,
tx_disparity_o
=>
from_phys
(
i
)
.
tx_disparity
,
tx_enc_err_o
=>
from_phys
(
i
)
.
tx_enc_err
,
rx_rbclk_o
=>
from_phys
(
i
)
.
rx_clk
,
rx_rbclk_sampled_o
=>
from_phys
(
i
)
.
rx_sampled_clk
,
rx_data_o
=>
from_phys
(
i
)
.
rx_data
,
rx_k_o
=>
from_phys
(
i
)
.
rx_k
,
rx_enc_err_o
=>
from_phys
(
i
)
.
rx_enc_err
,
rx_bitslide_o
=>
from_phys
(
i
)
.
rx_bitslide
,
rst_i
=>
to_phys
(
i
)
.
rst
,
debug_o
=>
from_phys
(
i
)
.
debug
,
debug_i
=>
to_phys
(
i
)
.
debug
,
loopen_i
=>
to_phys
(
i
)
.
loopen
,
pad_txn_o
=>
gtx_txn_o
(
i
),
pad_txp_o
=>
gtx_txp_o
(
i
),
...
...
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