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White Rabbit Switch - Gateware
Commits
81f37c2f
Commit
81f37c2f
authored
Jul 14, 2015
by
Grzegorz Daniluk
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Plain Diff
feed softpll with locked signals from plls multiplying ext. 10MHz in to 62.5MHz
parent
c03875dc
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9 changed files
with
52 additions
and
23 deletions
+52
-23
wr-cores
ip_cores/wr-cores
+1
-1
wrsw_rt_subsystem.vhd
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+3
-0
ext_pll_100_to_62m.vhd
platform/xilinx/ext_pll_100_to_62m.vhd
+5
-4
ext_pll_10_to_100.vhd
platform/xilinx/ext_pll_10_to_100.vhd
+5
-4
scb_top_bare.vhd
top/bare_top/scb_top_bare.vhd
+2
-0
wrsw_components_pkg.vhd
top/bare_top/wrsw_components_pkg.vhd
+2
-0
wrsw_top_pkg.vhd
top/bare_top/wrsw_top_pkg.vhd
+1
-0
scb_top_synthesis.vhd
top/scb_18ports/scb_top_synthesis.vhd
+17
-7
scb_top_synthesis.vhd
top/scb_8ports/scb_top_synthesis.vhd
+16
-7
No files found.
wr-cores
@
04583a97
Subproject commit
477ea639649c47cee6812ae25b48907b1abdfeb4
Subproject commit
04583a97d647a95219cc27012a586f1a8974d426
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @
81f37c2f
...
...
@@ -55,6 +55,7 @@ entity wrsw_rt_subsystem is
clk_rx_i
:
in
std_logic_vector
(
g_num_rx_clocks
-1
downto
0
);
clk_ext_i
:
in
std_logic
;
clk_ext_mul_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_500_o
:
out
std_logic
;
...
...
@@ -147,6 +148,7 @@ architecture rtl of wrsw_rt_subsystem is
clk_dmtd_i
:
in
std_logic
;
clk_ext_i
:
in
std_logic
;
clk_ext_mul_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
;
pps_csync_p1_i
:
in
std_logic
;
pps_ext_a_i
:
in
std_logic
;
dac_dmtd_data_o
:
out
std_logic_vector
(
15
downto
0
);
...
...
@@ -353,6 +355,7 @@ begin -- rtl
clk_dmtd_i
=>
clk_dmtd_i
,
clk_ext_i
=>
clk_ext_i
,
clk_ext_mul_i
=>
clk_ext_mul_i
,
clk_ext_mul_locked_i
=>
clk_ext_mul_locked_i
,
pps_csync_p1_i
=>
pps_csync
,
pps_ext_a_i
=>
pps_ext_i
,
dac_dmtd_data_o
=>
dac_dmtd_data
,
...
...
platform/xilinx/ext_pll_100_to_62m.vhd
View file @
81f37c2f
...
...
@@ -78,13 +78,14 @@ port
-- Clock out ports
clk_ext_mul_o
:
out
std_logic
;
-- Status and control signals
rst_a_i
:
in
std_logic
rst_a_i
:
in
std_logic
;
locked_o
:
out
std_logic
);
end
ext_pll_100_to_62m
;
architecture
xilinx
of
ext_pll_100_to_62m
is
attribute
CORE_GENERATION_INFO
:
string
;
attribute
CORE_GENERATION_INFO
of
xilinx
:
architecture
is
"ext_pll_100_to_62m,clk_wiz_v3_6,{component_name=ext_pll_100_to_62m,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=
fals
e,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}"
;
attribute
CORE_GENERATION_INFO
of
xilinx
:
architecture
is
"ext_pll_100_to_62m,clk_wiz_v3_6,{component_name=ext_pll_100_to_62m,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=
tru
e,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}"
;
-- Input clock buffering / unused connectors
signal
clkin1
:
std_logic
;
-- Output clock buffering / unused connectors
...
...
@@ -107,13 +108,13 @@ architecture xilinx of ext_pll_100_to_62m is
-- Dynamic phase shift unused signals
signal
psdone_unused
:
std_logic
;
-- Unused status signals
signal
locked_unused
:
std_logic
;
signal
clkfbstopped_unused
:
std_logic
;
signal
clkinstopped_unused
:
std_logic
;
begin
-- Input buffering
--------------------------------------
clkin1
<=
clk_ext_100_i
;
...
...
@@ -174,7 +175,7 @@ begin
PSINCDEC
=>
'0'
,
PSDONE
=>
psdone_unused
,
-- Other control and status signals
LOCKED
=>
locked_
unused
,
LOCKED
=>
locked_
o
,
CLKINSTOPPED
=>
clkinstopped_unused
,
CLKFBSTOPPED
=>
clkfbstopped_unused
,
PWRDWN
=>
'0'
,
...
...
platform/xilinx/ext_pll_10_to_100.vhd
View file @
81f37c2f
...
...
@@ -78,13 +78,14 @@ port
-- Clock out ports
clk_ext_100_o
:
out
std_logic
;
-- Status and control signals
rst_a_i
:
in
std_logic
rst_a_i
:
in
std_logic
;
locked_o
:
out
std_logic
);
end
ext_pll_10_to_100
;
architecture
xilinx
of
ext_pll_10_to_100
is
attribute
CORE_GENERATION_INFO
:
string
;
attribute
CORE_GENERATION_INFO
of
xilinx
:
architecture
is
"ext_pll_10_to_100,clk_wiz_v3_6,{component_name=ext_pll_10_to_100,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=100.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=
fals
e,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}"
;
attribute
CORE_GENERATION_INFO
of
xilinx
:
architecture
is
"ext_pll_10_to_100,clk_wiz_v3_6,{component_name=ext_pll_10_to_100,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=100.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=
tru
e,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}"
;
-- Input clock buffering / unused connectors
signal
clkin1
:
std_logic
;
-- Output clock buffering / unused connectors
...
...
@@ -107,13 +108,13 @@ architecture xilinx of ext_pll_10_to_100 is
-- Dynamic phase shift unused signals
signal
psdone_unused
:
std_logic
;
-- Unused status signals
signal
locked_unused
:
std_logic
;
signal
clkfbstopped_unused
:
std_logic
;
signal
clkinstopped_unused
:
std_logic
;
begin
-- Input buffering
--------------------------------------
clkin1
<=
clk_ext_i
;
...
...
@@ -174,7 +175,7 @@ begin
PSINCDEC
=>
'0'
,
PSDONE
=>
psdone_unused
,
-- Other control and status signals
LOCKED
=>
locked_
unused
,
LOCKED
=>
locked_
o
,
CLKINSTOPPED
=>
clkinstopped_unused
,
CLKFBSTOPPED
=>
clkfbstopped_unused
,
PWRDWN
=>
'0'
,
...
...
top/bare_top/scb_top_bare.vhd
View file @
81f37c2f
...
...
@@ -83,6 +83,7 @@ entity scb_top_bare is
clk_aux_i
:
in
std_logic
;
clk_ext_mul_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
;
clk_aux_p_o
:
out
std_logic
;
-- going to CLK2 SMC on the front pannel, by
clk_aux_n_o
:
out
std_logic
;
-- default it's 10MHz, but is configurable
...
...
@@ -513,6 +514,7 @@ begin
clk_rx_i
=>
clk_rx_vec
,
clk_ext_i
=>
pll_status_i
,
-- FIXME: UGLY HACK
clk_ext_mul_i
=>
clk_ext_mul_i
,
clk_ext_mul_locked_i
=>
clk_ext_mul_locked_i
,
clk_aux_p_o
=>
clk_aux_p_o
,
clk_aux_n_o
=>
clk_aux_n_o
,
clk_500_o
=>
clk_500_o
,
...
...
top/bare_top/wrsw_components_pkg.vhd
View file @
81f37c2f
...
...
@@ -206,6 +206,8 @@ package wrsw_components_pkg is
clk_dmtd_i
:
in
std_logic
;
clk_rx_i
:
in
std_logic_vector
(
g_num_rx_clocks
-1
downto
0
);
clk_aux_i
:
in
std_logic
;
clk_ext_mul_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_500_o
:
out
std_logic
;
...
...
top/bare_top/wrsw_top_pkg.vhd
View file @
81f37c2f
...
...
@@ -208,6 +208,7 @@ package wrsw_top_pkg is
clk_rx_i
:
in
std_logic_vector
(
g_num_rx_clocks
-1
downto
0
);
clk_ext_i
:
in
std_logic
;
clk_ext_mul_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_500_o
:
out
std_logic
;
...
...
top/scb_18ports/scb_top_synthesis.vhd
View file @
81f37c2f
...
...
@@ -199,14 +199,16 @@ architecture Behavioral of scb_top_synthesis is
port
(
clk_ext_i
:
in
std_logic
;
clk_ext_100_o
:
out
std_logic
;
rst_a_i
:
in
std_logic
);
rst_a_i
:
in
std_logic
;
locked_o
:
out
std_logic
);
end
component
;
component
ext_pll_100_to_62m
is
port
(
clk_ext_100_i
:
in
std_logic
;
clk_ext_mul_o
:
out
std_logic
;
rst_a_i
:
in
std_logic
);
rst_a_i
:
in
std_logic
;
locked_o
:
out
std_logic
);
end
component
;
...
...
@@ -292,6 +294,9 @@ architecture Behavioral of scb_top_synthesis is
signal
local_reset
,
ext_pll_reset
:
std_logic
;
signal
clk_ext
,
clk_ext_mul
:
std_logic
;
signal
clk_ext_100
:
std_logic
;
signal
ext_pll_100_locked
,
ext_pll_62_locked
:
std_logic
;
signal
clk_ext_mul_locked
:
std_logic
;
component
scb_top_bare
generic
(
g_num_ports
:
integer
;
...
...
@@ -311,6 +316,7 @@ architecture Behavioral of scb_top_synthesis is
clk_dmtd_i
:
in
std_logic
;
clk_aux_i
:
in
std_logic
;
clk_ext_mul_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_sys_o
:
out
std_logic
;
...
...
@@ -525,14 +531,17 @@ begin
port
map
(
clk_ext_i
=>
clk_ext
,
clk_ext_100_o
=>
clk_ext_100
,
rst_a_i
=>
ext_pll_reset
);
rst_a_i
=>
ext_pll_reset
,
locked_o
=>
ext_pll_100_locked
);
U_Ext_PLL2
:
ext_pll_100_to_62m
port
map
(
clk_ext_100_i
=>
clk_ext_100
,
clk_ext_mul_o
=>
clk_ext_mul
,
rst_a_i
=>
ext_pll_reset
);
rst_a_i
=>
ext_pll_reset
,
locked_o
=>
ext_pll_62_locked
);
clk_ext_mul_locked
<=
ext_pll_100_locked
and
ext_pll_62_locked
;
local_reset
<=
not
sys_rst_n_i
;
U_Extend_EXT_Reset
:
gc_extend_pulse
...
...
@@ -700,6 +709,7 @@ begin
clk_sys_o
=>
clk_sys
,
clk_aux_i
=>
clk_aux
,
clk_ext_mul_i
=>
clk_ext_mul
,
clk_ext_mul_locked_i
=>
clk_ext_mul_locked
,
clk_aux_p_o
=>
clk_aux_p_o
,
clk_aux_n_o
=>
clk_aux_n_o
,
cpu_wb_i
=>
top_master_out
,
...
...
top/scb_8ports/scb_top_synthesis.vhd
View file @
81f37c2f
...
...
@@ -210,14 +210,16 @@ architecture Behavioral of scb_top_synthesis is
port
(
clk_ext_i
:
in
std_logic
;
clk_ext_100_o
:
out
std_logic
;
rst_a_i
:
in
std_logic
);
rst_a_i
:
in
std_logic
;
locked_o
:
out
std_logic
);
end
component
;
component
ext_pll_100_to_62m
is
port
(
clk_ext_100_i
:
in
std_logic
;
clk_ext_mul_o
:
out
std_logic
;
rst_a_i
:
in
std_logic
);
rst_a_i
:
in
std_logic
;
locked_o
:
out
std_logic
);
end
component
;
...
...
@@ -300,6 +302,8 @@ architecture Behavioral of scb_top_synthesis is
signal
local_reset
,
ext_pll_reset
:
std_logic
;
signal
clk_ext
,
clk_ext_mul
:
std_logic
;
signal
clk_ext_100
:
std_logic
;
signal
ext_pll_100_locked
,
ext_pll_62_locked
:
std_logic
;
signal
clk_ext_mul_locked
:
std_logic
;
component
scb_top_bare
generic
(
...
...
@@ -320,6 +324,7 @@ architecture Behavioral of scb_top_synthesis is
clk_dmtd_i
:
in
std_logic
;
clk_aux_i
:
in
std_logic
;
clk_ext_mul_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_500_o
:
out
std_logic
;
...
...
@@ -538,14 +543,17 @@ begin
port
map
(
clk_ext_i
=>
clk_ext
,
clk_ext_100_o
=>
clk_ext_100
,
rst_a_i
=>
ext_pll_reset
);
rst_a_i
=>
ext_pll_reset
,
locked_o
=>
ext_pll_100_locked
);
U_Ext_PLL2
:
ext_pll_100_to_62m
port
map
(
clk_ext_100_i
=>
clk_ext_100
,
clk_ext_mul_o
=>
clk_ext_mul
,
rst_a_i
=>
ext_pll_reset
);
rst_a_i
=>
ext_pll_reset
,
locked_o
=>
ext_pll_62_locked
);
clk_ext_mul_locked
<=
ext_pll_100_locked
and
ext_pll_62_locked
;
dbg_clk_ext_o
<=
clk_ext_mul
;
local_reset
<=
not
sys_rst_n_i
;
...
...
@@ -715,6 +723,7 @@ begin
clk_sys_o
=>
clk_sys
,
clk_aux_i
=>
clk_aux
,
clk_ext_mul_i
=>
clk_ext_mul
,
clk_ext_mul_locked_i
=>
clk_ext_mul_locked
,
clk_aux_p_o
=>
clk_aux_p_o
,
clk_aux_n_o
=>
clk_aux_n_o
,
clk_500_o
=>
clk_500_o
,
...
...
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