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White Rabbit Switch - Gateware
Commit 72a35829 authored by li hongming's avatar li hongming
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Merge remote-tracking branch 'origin/hm-wrsfl-lowjitter' into hm-wrslj-pts 

 PTS for WRS-LJ which is normal WRS with external AD9516 for 10MHz input.
parents 7c945d5a c9e54723
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.gitignore
View file @ 72a35829
......@@ -13,3 +13,4 @@ fifo_generator_v6_1
build_wb.sh
doc/
synthesis_descriptor.vhd
*.en
Manifest.py
View file @ 72a35829
......@@ -7,8 +7,8 @@ modules = { "local" : [
"modules/wrsw_tru",
"modules/wrsw_tatsu",
"modules/wrsw_pstats",
"modules/wrsw_hwiu",
"modules/wrsw_watchdog",
"modules/wrsw_hwiu",
"modules/wrsw_watchdog",
"platform/virtex6/chipscope",
"platform/xilinx"],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git" ]
......
wr-cores @ 78c35cb0
Subproject commit 6f6b4404cf41821460c5b355ac0467cbae9afa30
Subproject commit 78c35cb0f0c396df415f1d35595c5593bbb717cc
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 72a35829
......@@ -58,7 +58,7 @@ entity wrsw_rt_subsystem is
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
-- clk_500_o : out std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
......@@ -94,8 +94,9 @@ entity wrsw_rt_subsystem is
-- TSCs are in sync with the master time counter and the timestamps are correct).
pps_valid_o : out std_logic;
pps_ext_i : in std_logic; -- external PPS input (from the front panel)
pps_ext_o : out std_logic; -- external PPS output (to the front panel)
pps_ext_i : in std_logic; -- external PPS input (from the front panel)
ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_ext_o : out std_logic; -- external PPS output (to the front panel)
sel_clk_sys_o : out std_logic; -- system clock selection: 0 = startup
-- clock, 1 = PLL clock
......@@ -120,8 +121,16 @@ entity wrsw_rt_subsystem is
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
-- WRS Low jitter AD9516
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic
-- Debug
spll_dbg_o : out std_logic_vector(5 downto 0)
-- spll_dbg_o : out std_logic_vector(5 downto 0)
);
end wrsw_rt_subsystem;
......@@ -161,7 +170,7 @@ architecture rtl of wrsw_rt_subsystem is
out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
debug_o : out std_logic_vector(5 downto 0);
-- debug_o : out std_logic_vector(5 downto 0);
dbg_fifo_irq_o : out std_logic);
end component;
......@@ -180,6 +189,7 @@ architecture rtl of wrsw_rt_subsystem is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
pps_valid_o : out std_logic;
......@@ -199,7 +209,7 @@ architecture rtl of wrsw_rt_subsystem is
pps_valid_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
-- clk_500_o : out std_logic;
ppsdel_tap_i : in std_logic_vector(4 downto 0);
ppsdel_tap_o : out std_logic_vector(4 downto 0);
ppsdel_tap_wr_o : out std_logic;
......@@ -216,8 +226,8 @@ architecture rtl of wrsw_rt_subsystem is
-- 0x10300 - 0x10400: GPIO
-- 0x10400 - 0x10500: Timer
constant c_NUM_GPIO_PINS : integer := 4;
constant c_NUM_WB_SLAVES : integer := 8;
constant c_NUM_GPIO_PINS : integer := 5;
constant c_NUM_WB_SLAVES : integer := 9;
constant c_MASTER_CPU : integer := 0;
constant c_MASTER_LM32 : integer := 1;
......@@ -230,7 +240,7 @@ architecture rtl of wrsw_rt_subsystem is
constant c_SLAVE_TIMER : integer := 5;
constant c_SLAVE_PPSGEN : integer := 6;
constant c_SLAVE_GEN10 : integer := 7;
constant c_SLAVE_SPI_EXT : integer := 8;
signal cnx_slave_in : t_wishbone_slave_in_array(1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(1 downto 0);
......@@ -354,9 +364,9 @@ begin -- rtl
clk_fb_i(0) => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
pps_csync_p1_i => pps_csync,
pps_csync_p1_i => pps_csync,
pps_ext_a_i => pps_ext_i,
dac_dmtd_data_o => dac_dmtd_data,
dac_dmtd_load_o => dac_dmtd_load,
......@@ -366,8 +376,9 @@ begin -- rtl
out_enable_i => "0",
out_locked_o => open,
slave_i => cnx_master_out(c_SLAVE_SOFTPLL),
slave_o => cnx_master_in(c_SLAVE_SOFTPLL),
debug_o => spll_dbg_o);
slave_o => cnx_master_in(c_SLAVE_SOFTPLL)
-- debug_o => spll_dbg_o
);
U_PPS_Gen : xwr_pps_gen
generic map (
......@@ -384,6 +395,7 @@ begin -- rtl
slave_i => cnx_master_out(c_SLAVE_PPSGEN),
slave_o => cnx_master_in(c_SLAVE_PPSGEN),
pps_in_i => pps_ext_i,
ppsin_term_o => ppsin_term_o,
pps_csync_o => pps_csync,
pps_out_o => pps_ext_o,
pps_valid_o => pps_valid,
......@@ -414,6 +426,25 @@ begin -- rtl
pad_sclk_o => pll_sck_o,
pad_mosi_o => pll_mosi_o,
pad_miso_i => pll_miso_i);
U_SPI_Master_external_board : xwb_spi
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_divider_len => 8,
g_max_char_len => 24,
g_num_slaves => 1)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => cnx_master_out(c_SLAVE_SPI_EXT),
slave_o => cnx_master_in(c_SLAVE_SPI_EXT),
desc_o => open,
pad_cs_o(0) => ext_pll_cs_n_o,
pad_sclk_o => ext_pll_sck_o,
pad_mosi_o => ext_pll_mosi_o,
pad_miso_i => ext_pll_miso_i);
U_GPIO : xwb_gpio_port
generic map (
......@@ -455,7 +486,7 @@ begin -- rtl
pps_valid_i => pps_valid,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
clk_500_o => clk_500_o,
-- clk_500_o => clk_500_o,
ppsdel_tap_i => ppsdel_tap_i,
ppsdel_tap_o => ppsdel_tap_o,
ppsdel_tap_wr_o => ppsdel_tap_wr_o,
......@@ -466,6 +497,8 @@ begin -- rtl
pll_reset_n_o <= gpio_out(1);
cpu_reset_n <= not gpio_out(2) and rst_n_i;
rst_n_o <= gpio_out(3);
ext_pll_reset_n_o <= gpio_out(4);
ext_pll_sync_n_o <= '1';
U_Main_DAC : gc_serial_dac
generic map (
......
syn/pts_scb/pts_scb.xise
View file @ 72a35829
......@@ -19,10 +19,10 @@
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="../../modules/wrsw_swcore/Switched-Multiported-RAM/utils.vh" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../modules/wrsw_swcore/Switched-Multiported-RAM/utils.vh" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
<properties>
......@@ -37,8 +37,8 @@
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
......@@ -51,7 +51,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-1" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-1" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -68,7 +68,7 @@
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="50" xil_pn:valueState="non-default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
......@@ -91,14 +91,14 @@
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -110,7 +110,7 @@
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
......@@ -125,9 +125,9 @@
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -161,18 +161,18 @@
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to System Monitor Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="Soft" xil_pn:valueState="non-default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Auto" xil_pn:valueState="non-default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Minimum Runtime" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Runtime Reduction with Multi-Threading;/opt/Xilinx/13.3/ISE_DS/ISE/virtex6/data/virtex6_runtime_multithreading.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
......@@ -182,11 +182,11 @@
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -206,21 +206,21 @@
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="pts_scb_top" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="ff1156" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Reentrant Route" xil_pn:valueState="non-default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="pts_scb_top_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="pts_scb_top_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="pts_scb_top_sim.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="pts_scb_top_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="pts_scb_top_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="pts_scb_top_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="pts_scb_top_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="pts_scb_top_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -238,20 +238,20 @@
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="pts_scb_top" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Error Report" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Error Report" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
......@@ -263,7 +263,7 @@
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -273,7 +273,7 @@
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
......@@ -313,13 +313,13 @@
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="No" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/13.3/ISE_DS/ISE/virtex6/data/virtex6_runtime_multithreading.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/virtex6/data/virtex6_area_with_physicalsynthesis.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -334,7 +334,7 @@
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="pts_scb" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -342,8 +342,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-01-11T16:12:13" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1A4D4649CF666ED7BAA8C2DBABE3B6A0" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2019-06-24T14:26:33" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2944273DD76B697A73F7BCAA0ABAB395" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
......@@ -355,10 +355,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="245"/>
<association xil_pn:name="Implementation" xil_pn:seqID="242"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="244"/>
<association xil_pn:name="Implementation" xil_pn:seqID="241"/>
</file>
<file xil_pn:name="../../platform/virtex6/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -385,7 +385,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_output.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
<file xil_pn:name="../../modules/wrsw_rtu/rtu_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
......@@ -394,16 +394,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../modules/wrsw_swcore/xswc_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="234"/>
<association xil_pn:name="Implementation" xil_pn:seqID="231"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/pts_scb/pts_wb_cpu_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="253"/>
<association xil_pn:name="Implementation" xil_pn:seqID="249"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -418,7 +418,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../modules/wrsw_rtu/pack_unpack_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
......@@ -436,7 +436,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/pts_scb/xwrsw_sandbox.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="227"/>
<association xil_pn:name="Implementation" xil_pn:seqID="224"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -460,7 +460,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_input.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
......@@ -496,7 +496,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../top/pts_scb/syst_mon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
<file xil_pn:name="../../modules/wrsw_swcore/Switched-Multiported-RAM/lvt_bin.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
......@@ -508,13 +508,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../platform/xilinx/ext_pll_100_to_62m.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="256"/>
<association xil_pn:name="Implementation" xil_pn:seqID="252"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../modules/wrsw_pstats/port_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
......@@ -523,10 +523,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../modules/wrsw_pstats/irq_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/gc_escape_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -538,49 +538,49 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="242"/>
<association xil_pn:name="Implementation" xil_pn:seqID="239"/>
</file>
<file xil_pn:name="../../modules/wrsw_swcore/Switched-Multiported-RAM/dpram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../modules/wrsw_tru/tru_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../../modules/wrsw_txtsu/xwrsw_txtsu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="231"/>
<association xil_pn:name="Implementation" xil_pn:seqID="228"/>
</file>
<file xil_pn:name="../../modules/wrsw_txtsu/wrsw_txtsu_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_read_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../platform/xilinx/ext_pll_10_to_100.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="255"/>
<association xil_pn:name="Implementation" xil_pn:seqID="251"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_free.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../modules/wrsw_pstats/pstats_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -592,22 +592,22 @@
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="223"/>
<association xil_pn:name="Implementation" xil_pn:seqID="220"/>
</file>
<file xil_pn:name="../../modules/wrsw_tatsu/wrsw_tatsu_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../../modules/wrsw_nic/nic_constants_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../modules/wrsw_swcore/swc_output_queue_scheduler.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xwr_transmission.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -616,7 +616,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../modules/wrsw_rtu/rtu_lookup_engine.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
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......@@ -631,22 +631,22 @@
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......@@ -658,19 +658,19 @@
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......@@ -679,10 +679,10 @@
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......@@ -697,22 +697,22 @@
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......@@ -721,19 +721,19 @@
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......@@ -745,16 +745,16 @@
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......@@ -763,7 +763,7 @@
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......@@ -778,34 +778,34 @@
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......@@ -814,16 +814,16 @@
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......@@ -838,10 +838,10 @@
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......@@ -862,7 +862,7 @@
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......@@ -877,10 +877,10 @@
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......@@ -895,7 +895,7 @@
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......@@ -913,10 +913,10 @@
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......@@ -940,7 +940,7 @@
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......@@ -949,25 +949,25 @@
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......@@ -988,34 +988,34 @@
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......@@ -1024,13 +1024,13 @@
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......@@ -1132,7 +1132,7 @@
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......@@ -1237,7 +1237,7 @@
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......@@ -1246,46 +1246,46 @@
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......@@ -1315,7 +1315,7 @@
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</file>
<file xil_pn:name="../../modules/wrsw_rtu/rtu_crc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1375,13 +1375,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../modules/wrsw_watchdog/wdog_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
<file xil_pn:name="../../modules/wrsw_swcore/swc_swcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../modules/wrsw_rtu/rtu_match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1402,7 +1402,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../top/pts_scb/wb_freq_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
......@@ -1417,10 +1417,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="219"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_write_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../modules/wrsw_tru/wrsw_tru_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1432,10 +1432,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/pts_scb/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="247"/>
<association xil_pn:name="Implementation" xil_pn:seqID="244"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1456,7 +1456,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
......@@ -1471,19 +1471,19 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../modules/wrsw_tru/tru_reconfig_rt_port_handler.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/pts_scb/wrsw_top_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="229"/>
<association xil_pn:name="Implementation" xil_pn:seqID="226"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1498,7 +1498,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../modules/wrsw_swcore/swc_ob_prio_queue.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
......@@ -1513,16 +1513,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../modules/wrsw_nic/nic_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../modules/wrsw_pstats/wrsw_pstats.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../../modules/wrsw_rtu/rtu_fast_match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../../modules/wrsw_swcore/swc_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1534,7 +1534,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../modules/wrsw_tru/tru_transition.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1543,16 +1543,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/pts_scb/swcore_pll.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="252"/>
<association xil_pn:name="Implementation" xil_pn:seqID="248"/>
</file>
<file xil_pn:name="../../modules/wrsw_rtu/PCK_CRC16_D16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
......
syn/scb_18ports/test_scb.xise
View file @ 72a35829
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/scb_8ports/test_scb.xise
View file @ 72a35829
This source diff could not be displayed because it is too large. You can view the blob instead.
top/bare_top/scb_top_bare.vhd
View file @ 72a35829
......@@ -81,9 +81,12 @@ entity scb_top_bare is
-- Programmable aux clock (from the AD9516 PLL output QDRII_200CLK). Used
-- for re-phasing the 10 MHz input as well as clocking the
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
-- External 10MHz clock input
clk_ext_i : in std_logic;
-- External 62.5MHz clock input (from 10MHz)
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic; -- going to CLK2 SMC on the front pannel, by
clk_aux_n_o : out std_logic; -- default it's 10MHz, but is configurable
......@@ -104,8 +107,9 @@ entity scb_top_bare is
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
......@@ -120,8 +124,7 @@ entity scb_top_bare is
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -129,6 +132,14 @@ entity scb_top_bare is
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
-- external AD9516 to mul 10MHz to 62.5MHz
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
......@@ -515,8 +526,8 @@ begin
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
......@@ -537,6 +548,7 @@ begin
pps_csync_o => pps_csync,
pps_valid_o => pps_valid,
pps_ext_i => pps_i,
ppsin_term_o=> ppsin_term_o,
pps_ext_o => pps_o_predelay,
sel_clk_sys_o => sel_clk_sys,
......@@ -556,6 +568,13 @@ begin
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
spll_dbg_o => spll_dbg_o);
U_DELAY_PPS: IODELAYE1
......
top/bare_top/wrs_sdb_pkg.vhd
View file @ 72a35829
......@@ -237,7 +237,7 @@ package wrs_sdb_pkg is
name => "WRSW SWCORE ")));
-- RT subsystem crossbar
constant c_rtbar_layout : t_sdb_record_array(7 downto 0) :=
constant c_rtbar_layout : t_sdb_record_array(8 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(16384), x"00000000"),
1 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00010000"), --UART
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00010100"), --SoftPLL
......@@ -245,7 +245,9 @@ package wrs_sdb_pkg is
4 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"00010300"), --GPIO
5 => f_sdb_embed_device(c_xwb_tics_sdb, x"00010400"), --TICS
6 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00010500"), --PPSgen
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"));--GEN 10MHz
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"), --GEN 10MHz
8 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010700")); --SPI ext
constant c_rtbar_sdb_address : t_wishbone_address := x"00010800";
constant c_rtbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_rtbar_layout, c_rtbar_sdb_address);
......
top/bare_top/wrsw_components_pkg.vhd
View file @ 72a35829
......@@ -153,6 +153,7 @@ package wrsw_components_pkg is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
......@@ -242,7 +243,13 @@ package wrsw_components_pkg is
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic);
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic);
end component;
component chipscope_icon
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 72a35829
......@@ -153,6 +153,7 @@ package wrsw_top_pkg is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
......@@ -231,6 +232,7 @@ package wrsw_top_pkg is
pps_csync_o : out std_logic;
pps_valid_o : out std_logic;
pps_ext_i : in std_logic;
ppsin_term_o : out std_logic;
pps_ext_o : out std_logic;
sel_clk_sys_o : out std_logic;
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others=>'0');
......@@ -246,6 +248,12 @@ package wrsw_top_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0));
end component;
......@@ -284,8 +292,9 @@ package wrsw_top_pkg is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out;
......@@ -298,13 +307,19 @@ package wrsw_top_pkg is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
......
top/pts_scb/pts_scb_top.ucf
View file @ 72a35829
This source diff could not be displayed because it is too large. You can view the blob instead.
top/pts_scb/pts_scb_top.vhd
View file @ 72a35829
......@@ -54,6 +54,7 @@ use UNISIM.vcomponents.all;
entity pts_scb_top is
generic(
g_cpu_addr_width : integer := 19;
g_with_ext_AD9516: boolean := true;
g_simulation : boolean := false
);
port (
......@@ -71,6 +72,9 @@ entity pts_scb_top is
fpga_clk_dmtd_p_i : in std_logic;
fpga_clk_dmtd_n_i : in std_logic;
-- External 10MHz input
clk_ext_i : in std_logic;
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
......@@ -101,8 +105,9 @@ entity pts_scb_top is
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
pps_i : in std_logic;
-- ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
......@@ -118,7 +123,6 @@ entity pts_scb_top is
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -128,7 +132,21 @@ entity pts_scb_top is
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- WRS Low Jitter board
-------------------------------------------------------------------------------
ext_clk_62mhz_p_i : in std_logic:='0';
ext_clk_62mhz_n_i : in std_logic:='0';
ext_pll_status_i : in std_logic:='0';
ext_pll_lock_i : in std_logic:='0';
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
-------------------------------------------------------------------------------
-- Clock fanout control
-------------------------------------------------------------------------------
......@@ -178,16 +196,13 @@ entity pts_scb_top is
sensors_scl_b: inout std_logic;
sensors_sda_b: inout std_logic;
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic;
-- mb_fan1_pwm_o : out std_logic;
-- mb_fan2_pwm_o : out std_logic;
---------------------------------------------------------------------------
-- PTS
---------------------------------------------------------------------------
clk_pck_i : in std_logic;
clk_10mhz_ext_i : in std_logic;
clk_25mhz_i : in std_logic;
pll_dmtd_clk_i : in std_logic;
pll_aux_clk_p_i : in std_logic;
pll_aux_clk_n_i : in std_logic;
pll_serdes_clk_p_i : in std_logic;
......@@ -271,8 +286,9 @@ architecture Behavioral of pts_scb_top is
signal clk_sys, clk_ref, clk_25mhz , clk_dmtd : std_logic;
signal pllout_clk_fb : std_logic;
attribute maxskew: string;
attribute maxskew of clk_dmtd : signal is "1.0ns";
--attribute maxskew: string;
--attribute maxskew of clk_dmtd : signal is "1.0ns";
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
......@@ -327,12 +343,14 @@ architecture Behavioral of pts_scb_top is
attribute buffer_type of clk_aux : signal is "BUFG";
attribute buffer_type of clk_sys : signal is "BUFG";
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal clk_ext_100 : std_logic;
signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic;
signal ext_clk_62mhz, ext_clk_62mhz_bufr : std_logic;
component pts_scb_top_bare
generic (
g_num_ports : integer;
......@@ -351,8 +369,9 @@ architecture Behavioral of pts_scb_top is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_sys_o : out std_logic;
......@@ -360,6 +379,7 @@ architecture Behavioral of pts_scb_top is
cpu_wb_o : out t_wishbone_slave_out;
cpu_irq_n_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic;
pps_o : out std_logic;
dac_helper_sync_n_o : out std_logic;
dac_helper_sclk_o : out std_logic;
......@@ -367,18 +387,23 @@ architecture Behavioral of pts_scb_top is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
uart_sel_o : out std_logic;
-- uart_sel_o : out std_logic;
clk_dmtd_divsel_o : out std_logic;
phys_o : out t_phyif_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
......@@ -392,9 +417,9 @@ architecture Behavioral of pts_scb_top is
i2c_sda_oen_o : out std_logic_vector(2 downto 0);
i2c_sda_o : out std_logic_vector(2 downto 0);
i2c_sda_i : in std_logic_vector(2 downto 0) := "111";
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0);
-- mb_fan1_pwm_o : out std_logic;
-- mb_fan2_pwm_o : out std_logic;
-- spll_dbg_o : out std_logic_vector(5 downto 0);
-- PTS
clk_pck_i : in std_logic;
clk_10mhz_ext_i : in std_logic;
......@@ -598,11 +623,36 @@ begin
CLKIN => clk_25mhz);
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
port map (
I => pll_status_i,
O => clk_ext);
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
port map (
I => clk_ext_i,
O => clk_ext);
gen_with_ext_AD9516 : if (g_with_ext_AD9516) generate
U_Buf_ext_clk_62mhz : IBUFDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => ext_clk_62mhz,
I => ext_clk_62mhz_p_i,
IB => ext_clk_62mhz_n_i);
U_Buf_ext_clk_62mhz_bufr : BUFR
port map (
CE => '1',
CLR => '0',
I => ext_clk_62mhz,
O => ext_clk_62mhz_bufr);
clk_ext_mul <= ext_clk_62mhz_bufr;
clk_ext_mul_locked <= ext_pll_lock_i; -- Fixme, connect to ext_pll_status
end generate gen_with_ext_AD9516;
gen_without_ext_AD9516 : if (not g_with_ext_AD9516) generate
U_Ext_PLL1: ext_pll_10_to_100
port map(
......@@ -620,15 +670,17 @@ begin
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
g_width => 1000)
port map(
clk_i => clk_sys,
rst_n_i => sys_rst_n_i,
pulse_i => local_reset,
extended_o => ext_pll_reset);
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
g_width => 1000)
port map(
clk_i => clk_sys,
rst_n_i => sys_rst_n_i,
pulse_i => local_reset,
extended_o => ext_pll_reset);
end generate gen_without_ext_AD9516;
------------------------------------------------
cmp_wb_cpu_bridge : wb_cpu_bridge
......@@ -776,7 +828,7 @@ begin
g_with_HWIU => true,
g_with_PSTATS => true,
g_with_muxed_CS => false,
g_with_watchdog => true,
g_with_watchdog => false,
g_inj_per_EP => "00" & x"0000")
port map (
sys_rst_n_i => sys_rst_n_i,
......@@ -785,7 +837,8 @@ begin
clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_mul_i => clk_ext_mul,
clk_ext_i => clk_ext,
clk_ext_mul_i => clk_ext_mul,
clk_ext_mul_locked_i=> clk_ext_mul_locked,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
......@@ -793,6 +846,7 @@ begin
cpu_wb_o => top_master_in,
cpu_irq_n_o => cpu_irq_n_o,
pps_i => pps_i,
-- ppsin_term_o => ppsin_term_o,
pps_o => pps_o,
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
......@@ -800,13 +854,18 @@ begin
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
pll_status_i => clk_ext,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
......@@ -824,9 +883,7 @@ begin
i2c_sda_oen_o => i2c_sda_oen,
i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in,
mb_fan1_pwm_o => mb_fan1_pwm_o,
mb_fan2_pwm_o => mb_fan2_pwm_o,
spll_dbg_o => open,
-- spll_dbg_o => open,
-- PTS
clk_pck_i => clk_pck,
clk_10mhz_ext_i => clk_ext,
......
top/pts_scb/pts_scb_top_bare.vhd
View file @ 72a35829
......@@ -82,14 +82,17 @@ entity pts_scb_top_bare is
-- Programmable aux clock (from the AD9516 PLL output QDRII_200CLK). Used
-- for re-phasing the 10 MHz input as well as clocking the
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
-- External 10MHz clock input
clk_ext_i : in std_logic;
-- External 62.5MHz clock input (from 10MHz)
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic; -- going to CLK2 SMC on the front pannel, by
clk_aux_n_o : out std_logic; -- default it's 10MHz, but is configurable
clk_500_o : out std_logic;
-- clk_500_o : out std_logic;
-- Muxed system clock
clk_sys_o : out std_logic;
......@@ -105,8 +108,9 @@ entity pts_scb_top_bare is
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
......@@ -121,8 +125,7 @@ entity pts_scb_top_bare is
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -130,6 +133,14 @@ entity pts_scb_top_bare is
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
-- external AD9516 to mul 10MHz to 62.5MHz
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
......@@ -179,10 +190,10 @@ entity pts_scb_top_bare is
-- Mini-backplane PWM fans
---------------------------------------------------------------------------
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic;
-- mb_fan1_pwm_o : out std_logic;
-- mb_fan2_pwm_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0);
-- spll_dbg_o : out std_logic_vector(5 downto 0);
---------------------------------------------------------------------------
-- PTS
......@@ -651,12 +662,12 @@ begin
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
clk_500_o => clk_500_o,
-- clk_500_o => clk_500_o,
rst_n_i => rst_n_sys,
rst_n_o => rst_n_periph,
wb_i => cnx_master_out(c_SLAVE_RT_SUBSYSTEM),
......@@ -673,6 +684,7 @@ begin
pps_csync_o => pps_csync,
pps_valid_o => pps_valid,
pps_ext_i => pps_i,
ppsin_term_o=> ppsin_term_o,
pps_ext_o => pps_out,
sel_clk_sys_o => sel_clk_sys,
......@@ -692,7 +704,15 @@ begin
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => open, -- pll_sync_n_o, -- not used within wrsw_rt_subsystem
pll_reset_n_o => pll_reset_n_o,
spll_dbg_o => spll_dbg_o);
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o
-- spll_dbg_o => spll_dbg_o
);
U_DELAY_PPS: IODELAYE1
generic map (
......@@ -789,12 +809,12 @@ begin
g_tx_force_gap_length => 0,
g_tx_runt_padding => false,
g_pcs_16bit => true,
g_rx_buffer_size => 1024,
g_rx_buffer_size => 1000,
g_with_rx_buffer => true,
g_with_flow_control => false,-- useless: flow control commented out
g_with_timestamper => true,
g_with_dpi_classifier => true,
g_with_vlans => true,
g_with_vlans => false,
g_with_rtu => true,
g_with_leds => true,
g_with_dmtd => false,
......@@ -940,12 +960,12 @@ begin
g_address_granularity => BYTE,
g_prio_num => 8,
g_output_queue_num => 8,
g_max_pck_size => 10 * 1024,
g_max_pck_size => 9 * 1024,
g_max_oob_size => 3,
g_num_ports => g_num_ports+1,
g_pck_pg_free_fifo_size => 512,
g_pck_pg_free_fifo_size => 256,
g_input_block_cannot_accept_data => "drop_pck",
g_output_block_per_queue_fifo_size=> 64,
g_output_block_per_queue_fifo_size=> 32,
g_wb_data_width => 16,
g_wb_addr_width => 2,
g_wb_sel_width => 2,
......@@ -1120,31 +1140,25 @@ begin
wb_i => cnx_master_out(c_SLAVE_TXTSU),
wb_o => cnx_master_in(c_SLAVE_TXTSU));
--TRIG2(15 downto 0) <= txtsu_timestamps(0).frame_id;
--TRIG2(21 downto 16) <= txtsu_timestamps(0).port_id;
--TRIG2(22) <= txtsu_timestamps(0).valid;
U_GPIO : xwb_gpio_port
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_pins => c_NUM_GPIO_PINS,
g_with_builtin_tristates => false)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_periph,
slave_i => cnx_master_out(c_SLAVE_GPIO),
slave_o => cnx_master_in(c_SLAVE_GPIO),
gpio_b => dummy,
gpio_out_o => gpio_out,
gpio_in_i => gpio_in);
uart_sel_o <= gpio_out(0);
gpio_o(0) <= gpio_out(0);
gpio_in(0) <= gpio_i(0);
-- U_GPIO : xwb_gpio_port
-- generic map (
-- g_interface_mode => PIPELINED,
-- g_address_granularity => BYTE,
-- g_num_pins => c_NUM_GPIO_PINS,
-- g_with_builtin_tristates => false)
-- port map (
-- clk_sys_i => clk_sys,
-- rst_n_i => rst_n_periph,
-- slave_i => cnx_master_out(c_SLAVE_GPIO),
-- slave_o => cnx_master_in(c_SLAVE_GPIO),
-- gpio_b => dummy,
-- gpio_out_o => gpio_out,
-- gpio_in_i => gpio_in
-- );
-- uart_sel_o <= gpio_out(0);
-- gpio_o(0) <= gpio_out(0);
-- gpio_in(0) <= gpio_i(0);
U_MiniBackplane_I2C : xwb_i2c_master
generic map (
......@@ -1234,22 +1248,22 @@ begin
-- PWM Controlle for mini-backplane fan drive
-----------------------------------------------------------------------------
U_PWM_Controller : xwb_simple_pwm
generic map (
g_num_channels => 2,
g_regs_size => 8,
g_default_period => 255,
g_default_presc => 30,
g_default_val => 255,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_periph,
slave_i => cnx_master_out(c_SLAVE_PWM),
slave_o => cnx_master_in(c_SLAVE_PWM),
pwm_o(0) => mb_fan1_pwm_o,
pwm_o(1) => mb_fan2_pwm_o);
-- U_PWM_Controller : xwb_simple_pwm
-- generic map (
-- g_num_channels => 2,
-- g_regs_size => 8,
-- g_default_period => 255,
-- g_default_presc => 30,
-- g_default_val => 255,
-- g_interface_mode => PIPELINED,
-- g_address_granularity => BYTE)
-- port map (
-- clk_sys_i => clk_sys,
-- rst_n_i => rst_n_periph,
-- slave_i => cnx_master_out(c_SLAVE_PWM),
-- slave_o => cnx_master_in(c_SLAVE_PWM),
-- pwm_o(0) => mb_fan1_pwm_o,
-- pwm_o(1) => mb_fan2_pwm_o);
-----------------------------------------------------------------------------
-- Interrupt assignment
......
top/pts_scb/wrs_sdb_pkg.vhd
View file @ 72a35829
......@@ -302,7 +302,7 @@ package wrs_sdb_pkg is
name => "WRSW SANDBOX ")));
-- RT subsystem crossbar
constant c_rtbar_layout : t_sdb_record_array(7 downto 0) :=
constant c_rtbar_layout : t_sdb_record_array(8 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(16384), x"00000000"),
1 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00010000"), --UART
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00010100"), --SoftPLL
......@@ -310,7 +310,9 @@ package wrs_sdb_pkg is
4 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"00010300"), --GPIO
5 => f_sdb_embed_device(c_xwb_tics_sdb, x"00010400"), --TICS
6 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00010500"), --PPSgen
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"));--GEN 10MHz
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"), --GEN 10MHz
8 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010700")); --SPI ext
constant c_rtbar_sdb_address : t_wishbone_address := x"00010800";
constant c_rtbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_rtbar_layout, c_rtbar_sdb_address);
......
top/pts_scb/wrsw_components_pkg.vhd
View file @ 72a35829
......@@ -153,6 +153,7 @@ package wrsw_components_pkg is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
......@@ -242,7 +243,13 @@ package wrsw_components_pkg is
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic);
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic);
end component;
component chipscope_icon
......
top/pts_scb/wrsw_top_pkg.vhd
View file @ 72a35829
......@@ -153,6 +153,7 @@ package wrsw_top_pkg is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
......@@ -215,7 +216,7 @@ package wrsw_top_pkg is
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
-- clk_500_o : out std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
wb_i : in t_wishbone_slave_in;
......@@ -231,6 +232,7 @@ package wrsw_top_pkg is
pps_csync_o : out std_logic;
pps_valid_o : out std_logic;
pps_ext_i : in std_logic;
ppsin_term_o : out std_logic;
pps_ext_o : out std_logic;
sel_clk_sys_o : out std_logic;
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others=>'0');
......@@ -246,7 +248,14 @@ package wrsw_top_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0));
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic
-- spll_dbg_o : out std_logic_vector(5 downto 0)
);
end component;
component chipscope_icon
......@@ -284,8 +293,9 @@ package wrsw_top_pkg is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out;
......@@ -298,13 +308,19 @@ package wrsw_top_pkg is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
......
top/scb_15ports/scb_top_synthesis.ucf
View file @ 72a35829
......@@ -13,6 +13,8 @@ NET "fpga_clk_aux_n_i" LOC=B10;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
NET "clk_ext_i" LOC=K13;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
......@@ -99,7 +101,7 @@ NET "pll_sck_o" LOC="AE16";
NET "pll_mosi_o" LOC="AH19";
NET "pll_miso_i" LOC="AJ19";
NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="K13";
# NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "uart_txd_o" LOC="E11";
......
top/scb_15ports/scb_top_synthesis.vhd
View file @ 72a35829
......@@ -74,6 +74,9 @@ entity scb_top_synthesis is
-- (from the AD9516 PLL output QDRII_200CLK)
fpga_clk_aux_p_i : in std_logic;
fpga_clk_aux_n_i : in std_logic;
-- External 10MHz input
clk_ext_i : in std_logic;
-------------------------------------------------------------------------------
-- Atmel EBI bus
......@@ -118,7 +121,7 @@ entity scb_top_synthesis is
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -291,7 +294,7 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -605,6 +608,7 @@ begin
clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_i => clk_ext_i,
cpu_wb_i => top_master_out,
cpu_wb_o => top_master_in,
cpu_irq_n_o => cpu_irq_n_o,
......@@ -616,7 +620,7 @@ begin
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
pll_status_i => pll_status_i,
-- pll_status_i => pll_status_i,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 72a35829
This source diff could not be displayed because it is too large. You can view the blob instead.
top/scb_18ports/scb_top_synthesis.vhd
View file @ 72a35829
......@@ -3,7 +3,7 @@
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : scb_top_synthesis.vhd
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk, Hongming
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2014-03-20
......@@ -53,6 +53,7 @@ use UNISIM.vcomponents.all;
entity scb_top_synthesis is
generic(
g_cpu_addr_width : integer := 19;
g_with_ext_AD9516: boolean := true;
g_simulation : boolean := false
);
port (
......@@ -70,9 +71,14 @@ entity scb_top_synthesis is
fpga_clk_dmtd_p_i : in std_logic;
fpga_clk_dmtd_n_i : in std_logic;
-- External 10MHz input
clk_ext_i : in std_logic;
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
-- clk_sys_dbg_o: out std_logic;
-------------------------------------------------------------------------------
-- Atmel EBI bus
......@@ -100,8 +106,9 @@ entity scb_top_synthesis is
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
......@@ -117,7 +124,6 @@ entity scb_top_synthesis is
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -127,7 +133,21 @@ entity scb_top_synthesis is
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- WRS Low Jitter board
-------------------------------------------------------------------------------
ext_clk_62mhz_p_i : in std_logic:='0';
ext_clk_62mhz_n_i : in std_logic:='0';
ext_pll_status_i : in std_logic:='0';
ext_pll_lock_i : in std_logic:='0';
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
-------------------------------------------------------------------------------
-- Clock fanout control
-------------------------------------------------------------------------------
......@@ -175,10 +195,10 @@ entity scb_top_synthesis is
mbl_sda_b : inout std_logic_vector(1 downto 0);
sensors_scl_b: inout std_logic;
sensors_sda_b: inout std_logic;
sensors_sda_b: inout std_logic
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic
-- mb_fan1_pwm_o : out std_logic;
-- mb_fan2_pwm_o : out std_logic
);
......@@ -291,12 +311,14 @@ architecture Behavioral of scb_top_synthesis is
attribute buffer_type of clk_aux : signal is "BUFG";
attribute buffer_type of clk_sys : signal is "BUFG";
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal clk_ext_100 : std_logic;
signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic;
signal ext_clk_62mhz, ext_clk_62mhz_bufr : std_logic;
component scb_top_bare
generic (
g_num_ports : integer;
......@@ -315,15 +337,18 @@ architecture Behavioral of scb_top_synthesis is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out;
cpu_irq_n_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic;
pps_o : out std_logic;
dac_helper_sync_n_o : out std_logic;
dac_helper_sclk_o : out std_logic;
......@@ -331,13 +356,18 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
......@@ -521,12 +551,36 @@ begin
CLKIN => clk_25mhz);
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
port map (
I => pll_status_i,
O => clk_ext);
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
port map (
I => clk_ext_i,
O => clk_ext);
gen_with_ext_AD9516 : if (g_with_ext_AD9516) generate
U_Buf_ext_clk_62mhz : IBUFGDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => ext_clk_62mhz,
I => ext_clk_62mhz_p_i,
IB => ext_clk_62mhz_n_i);
U_Buf_ext_clk_62mhz_bufr : BUFR
port map (
CE => '1',
CLR => '0',
I => ext_clk_62mhz,
O => ext_clk_62mhz_bufr);
clk_ext_mul <= ext_clk_62mhz_bufr;
clk_ext_mul_locked <= ext_pll_lock_i; -- Fixme, connect to ext_pll_status
end generate gen_with_ext_AD9516;
gen_without_ext_AD9516 : if (not g_with_ext_AD9516) generate
U_Ext_PLL1: ext_pll_10_to_100
port map(
clk_ext_i => clk_ext,
......@@ -543,15 +597,16 @@ begin
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
g_width => 1000)
port map(
clk_i => clk_sys,
rst_n_i => sys_rst_n_i,
pulse_i => local_reset,
extended_o => ext_pll_reset);
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
g_width => 1000)
port map(
clk_i => clk_sys,
rst_n_i => sys_rst_n_i,
pulse_i => local_reset,
extended_o => ext_pll_reset);
end generate gen_without_ext_AD9516;
------------------------------------------------
cmp_wb_cpu_bridge : wb_cpu_bridge
......@@ -708,14 +763,17 @@ begin
clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_mul_i => clk_ext_mul,
clk_ext_i => clk_ext,
clk_ext_mul_i => clk_ext_mul,
clk_ext_mul_locked_i=> clk_ext_mul_locked,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
clk_500_o => clk_500_o,
cpu_wb_i => top_master_out,
cpu_wb_o => top_master_in,
cpu_irq_n_o => cpu_irq_n_o,
pps_i => pps_i,
ppsin_term_o => ppsin_term_o,
pps_o => pps_o,
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
......@@ -723,13 +781,18 @@ begin
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
pll_status_i => clk_ext,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
......@@ -747,8 +810,8 @@ begin
i2c_sda_oen_o => i2c_sda_oen,
i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in,
mb_fan1_pwm_o => mb_fan1_pwm_o,
mb_fan2_pwm_o => mb_fan2_pwm_o,
-- mb_fan1_pwm_o => mb_fan1_pwm_o,
-- mb_fan2_pwm_o => mb_fan2_pwm_o,
spll_dbg_o => open);
i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
......
top/scb_8ports/scb_top_synthesis.ucf
View file @ 72a35829
......@@ -10,10 +10,14 @@ NET "fpga_clk_ref_n_i" LOC=H9;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
NET "clk_ext_i" LOC=K13;
NET "clk_aux_p_o" LOC=B20;
NET "clk_aux_n_o" LOC=C19;
NET "clk_500_o" LOC=AM33;
NET "clk_sys_dbg_o" LOC=AL33;
# NET "clk_sys_dbg_o" LOC=AL33;
NET "ext_clk_62mhz_p_i" LOC = AN33;
NET "ext_clk_62mhz_n_i" LOC = AN34;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
......@@ -94,6 +98,8 @@ NET "cpu_data_b<0>" LOC="A33";
NET "pps_i" LOC="J25";
NET "ppsin_term_o" LOC="AL34";
NET "ppsin_term_o" IOSTANDARD="LVCMOS25";
NET "pps_o" LOC="U23";
NET "dac_helper_sync_n_o" LOC="AD17";
......@@ -109,9 +115,17 @@ NET "pll_sck_o" LOC="AE16";
NET "pll_mosi_o" LOC="AH19";
NET "pll_miso_i" LOC="AJ19";
NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="K13";
# NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "ext_pll_cs_n_o" LOC = AD27;
NET "ext_pll_sck_o" LOC = AD26;
NET "ext_pll_mosi_o" LOC = AE27;
NET "ext_pll_miso_i" LOC = AF28;
NET "ext_pll_reset_n_o" LOC = AF29;
NET "ext_pll_status_i" LOC = AD25;
NET "ext_pll_sync_n_o" LOC = AJ34;
NET "uart_txd_o" LOC="E11";
NET "uart_rxd_i" LOC="D11";
......@@ -131,17 +145,17 @@ NET "clk_sel_o" LOC="AK17";
#NET "gtx4_7_clk_n_i" IOSTANDARD="LVPECL_25";
#NET "gtx4_7_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx8_11_clk_n_i" LOC="V5";
NET "gtx8_11_clk_p_i" LOC="V6";
# NET "gtx8_11_clk_n_i" LOC="V5";
# NET "gtx8_11_clk_p_i" LOC="V6";
NET "gtx8_11_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx8_11_clk_p_i" IOSTANDARD="LVPECL_25";
# NET "gtx8_11_clk_n_i" IOSTANDARD="LVPECL_25";
# NET "gtx8_11_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx12_15_clk_n_i" LOC="P5";
NET "gtx12_15_clk_p_i" LOC="P6";
# NET "gtx12_15_clk_n_i" LOC="P5";
# NET "gtx12_15_clk_p_i" LOC="P6";
NET "gtx12_15_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx12_15_clk_p_i" IOSTANDARD="LVPECL_25";
# NET "gtx12_15_clk_n_i" IOSTANDARD="LVPECL_25";
# NET "gtx12_15_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx16_19_clk_n_i" LOC="H5";
NET "gtx16_19_clk_p_i" LOC="H6";
......@@ -149,7 +163,6 @@ NET "gtx16_19_clk_p_i" LOC="H6";
NET "gtx16_19_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx_rxp_i[0]" LOC="AP5"; # gtx0
#NET "gtx_rxn_i[0]" LOC="AP6";
......@@ -210,41 +223,41 @@ NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx_txp_o[9]" LOC="V1";
#NET "gtx_txn_o[9]" LOC="V2";
NET "gtx_rxp_i[7]" LOC="U3";
NET "gtx_rxn_i[7]" LOC="U4";
# NET "gtx_rxp_i[7]" LOC="U3";
# NET "gtx_rxn_i[7]" LOC="U4";
NET "gtx_txp_o[7]" LOC="T1";
NET "gtx_txn_o[7]" LOC="T2";
# NET "gtx_txp_o[7]" LOC="T1";
# NET "gtx_txn_o[7]" LOC="T2";
NET "gtx_rxp_i[6]" LOC="R3";
NET "gtx_rxn_i[6]" LOC="R4";
# NET "gtx_rxp_i[6]" LOC="R3";
# NET "gtx_rxn_i[6]" LOC="R4";
NET "gtx_txp_o[6]" LOC="P1";
NET "gtx_txn_o[6]" LOC="P2";
# NET "gtx_txp_o[6]" LOC="P1";
# NET "gtx_txn_o[6]" LOC="P2";
NET "gtx_rxp_i[5]" LOC="N3";
NET "gtx_rxn_i[5]" LOC="N4";
# NET "gtx_rxp_i[5]" LOC="N3";
# NET "gtx_rxn_i[5]" LOC="N4";
NET "gtx_txp_o[5]" LOC="M1";
NET "gtx_txn_o[5]" LOC="M2";
# NET "gtx_txp_o[5]" LOC="M1";
# NET "gtx_txn_o[5]" LOC="M2";
NET "gtx_rxp_i[4]" LOC="L3";
NET "gtx_rxn_i[4]" LOC="L4";
# NET "gtx_rxp_i[4]" LOC="L3";
# NET "gtx_rxn_i[4]" LOC="L4";
NET "gtx_txp_o[4]" LOC="K1";
NET "gtx_txn_o[4]" LOC="K2";
# NET "gtx_txp_o[4]" LOC="K1";
# NET "gtx_txn_o[4]" LOC="K2";
NET "gtx_rxp_i[3]" LOC="K5"; #gtx14
NET "gtx_rxn_i[3]" LOC="K6";
# NET "gtx_rxp_i[3]" LOC="K5"; #gtx14
# NET "gtx_rxn_i[3]" LOC="K6";
NET "gtx_txp_o[3]" LOC="H1";
NET "gtx_txn_o[3]" LOC="H2";
# NET "gtx_txp_o[3]" LOC="H1";
# NET "gtx_txn_o[3]" LOC="H2";
NET "gtx_rxp_i[2]" LOC="J3"; # gtx15
NET "gtx_rxn_i[2]" LOC="J4";
# NET "gtx_rxp_i[2]" LOC="J3"; # gtx15
# NET "gtx_rxn_i[2]" LOC="J4";
NET "gtx_txp_o[2]" LOC="F1";
NET "gtx_txn_o[2]" LOC="F2";
# NET "gtx_txp_o[2]" LOC="F1";
# NET "gtx_txn_o[2]" LOC="F2";
NET "gtx_rxp_i[1]" LOC="G3"; # gtx16
NET "gtx_rxn_i[1]" LOC="G4";
......@@ -260,111 +273,211 @@ NET "gtx_txn_o[0]" LOC="C4";
NET "led_act_o[0]" LOC="AE33";
NET "led_act_o[1]" LOC="AE34";
NET "led_act_o[2]" LOC="AB30";
NET "led_act_o[3]" LOC="AC30";
# NET "led_act_o[2]" LOC="AB30";
# NET "led_act_o[3]" LOC="AC30";
NET "led_act_o[4]" LOC="AA26";
NET "led_act_o[5]" LOC="AA25";
NET "led_act_o[6]" LOC="AB27";
NET "led_act_o[7]" LOC="AC27";
# NET "led_act_o[4]" LOC="AA26";
# NET "led_act_o[5]" LOC="AA25";
# NET "led_act_o[6]" LOC="AB27";
# NET "led_act_o[7]" LOC="AC27";
NET "clk_dmtd_divsel_o" LOC="AN15";
NET "mbl_scl_b[0]" LOC="AF31";
NET "mbl_sda_b[0]" LOC="AG32";
NET "mbl_scl_b[1]" LOC="AC25";
NET "mbl_sda_b[1]" LOC="AG31";
NET "mb_fan1_pwm_o" LOC="C12";
NET "mb_fan2_pwm_o" LOC="D12";
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/20
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/22
NET "fpga_clk_25mhz_n_i" TNM_NET = fpga_clk_25mhz_n_i;
TIMESPEC TS_fpga_clk_25mhz_n_i = PERIOD "fpga_clk_25mhz_n_i" 40 ns HIGH 50%;
NET "fpga_clk_25mhz_p_i" TNM_NET = fpga_clk_25mhz_p_i;
TIMESPEC TS_fpga_clk_25mhz_p_i = PERIOD "fpga_clk_25mhz_p_i" 40 ns HIGH 50%;
NET "fpga_clk_dmtd_n_i" TNM_NET = fpga_clk_dmtd_n_i;
TIMESPEC TS_fpga_clk_dmtd_n_i = PERIOD "fpga_clk_dmtd_n_i" 16 ns HIGH 50%;
NET "fpga_clk_dmtd_p_i" TNM_NET = fpga_clk_dmtd_p_i;
TIMESPEC TS_fpga_clk_dmtd_p_i = PERIOD "fpga_clk_dmtd_p_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_n_i" TNM_NET = fpga_clk_ref_n_i;
TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
#NET "gen_phys[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_0__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[1].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_1__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[1].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[2].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[2].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[3].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[4].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[4].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[4].U_PHY/tx_out_clk_bufin;
#TIMESPEC TS_gen_phys_4__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[4].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[5].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[5].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_5__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[5].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[6].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[6].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_6__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[6].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[7].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[7].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_7__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[7].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[8].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[8].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[8].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[8].U_PHY/tx_out_clk_bufin;
#TIMESPEC TS_gen_phys_8__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[8].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[9].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[9].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_9__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[9].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[10].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[10].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_10__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[10].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[11].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[11].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_11__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[11].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[12].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[12].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_12__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[12].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[13].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[13].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_13__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[13].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[14].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[14].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_14__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[14].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[15].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[15].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_15__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[15].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[16].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[16].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_16__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[16].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[16].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[16].U_PHY/tx_out_clk_bufin;
#TIMESPEC TS_gen_phys_16__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[16].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[17].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[17].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_17__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[17].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gtx0_3_clk_n_i" TNM_NET = gtx0_3_clk_n_i;
#TIMESPEC TS_gtx0_3_clk_n_i = PERIOD "gtx0_3_clk_n_i" 8 ns HIGH 50%;
#NET "gtx0_3_clk_p_i" TNM_NET = gtx0_3_clk_p_i;
#TIMESPEC TS_gtx0_3_clk_p_i = PERIOD "gtx0_3_clk_p_i" 8 ns HIGH 50%;
#NET "gtx4_7_clk_n_i" TNM_NET = gtx4_7_clk_n_i;
#TIMESPEC TS_gtx4_7_clk_n_i = PERIOD "gtx4_7_clk_n_i" 8 ns HIGH 50%;
#NET "gtx4_7_clk_p_i" TNM_NET = gtx4_7_clk_p_i;
#TIMESPEC TS_gtx4_7_clk_p_i = PERIOD "gtx4_7_clk_p_i" 8 ns HIGH 50%;
#NET "gtx8_11_clk_n_i" TNM_NET = gtx8_11_clk_n_i;
#TIMESPEC TS_gtx8_11_clk_n_i = PERIOD "gtx8_11_clk_n_i" 8 ns HIGH 50%;
#NET "gtx8_11_clk_p_i" TNM_NET = gtx8_11_clk_p_i;
#TIMESPEC TS_gtx8_11_clk_p_i = PERIOD "gtx8_11_clk_p_i" 8 ns HIGH 50%;
NET "gtx12_15_clk_n_i" TNM_NET = gtx12_15_clk_n_i;
TIMESPEC TS_gtx12_15_clk_n_i = PERIOD "gtx12_15_clk_n_i" 8 ns HIGH 50%;
NET "gtx12_15_clk_p_i" TNM_NET = gtx12_15_clk_p_i;
TIMESPEC TS_gtx12_15_clk_p_i = PERIOD "gtx12_15_clk_p_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_n_i" TNM_NET = gtx16_19_clk_n_i;
TIMESPEC TS_gtx16_19_clk_n_i = PERIOD "gtx16_19_clk_n_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
#NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17
# NET "mb_fan1_pwm_o" LOC="C12";
# NET "mb_fan2_pwm_o" LOC="D12";
# clock period
NET "clk_25mhz" TNM_NET = fpga_clk_25mhz;
NET "clk_dmtd" TNM_NET = fpga_clk_dmtd;
NET "clk_ref" TNM_NET = fpga_clk_ref;
#NET "clk_gtx0_3" TNM_NET = gtx0_3_clk;
#NET "clk_gtx4_7" TNM_NET = gtx4_7_clk;
#NET "clk_gtx8_11" TNM_NET = gtx8_11_clk;
#NET "clk_gtx12_15" TNM_NET = gtx12_15_clk;
NET "clk_gtx16_19" TNM_NET = gtx16_19_clk;
TIMESPEC TS_fpga_clk_25mhz = PERIOD "fpga_clk_25mhz" 40ns HIGH 50%;
TIMESPEC TS_fpga_clk_dmtd = PERIOD "fpga_clk_dmtd" 16ns HIGH 50%;
TIMESPEC TS_fpga_clk_ref = PERIOD "fpga_clk_ref" 16ns HIGH 50%;
#TIMESPEC TS_gtx0_3_clk = PERIOD "gtx0_3_clk" 8ns HIGH 50%;
#TIMESPEC TS_gtx4_7_clk = PERIOD "gtx4_7_clk" 8ns HIGH 50%;
#TIMESPEC TS_gtx8_11_clk = PERIOD "gtx8_11_clk" 8ns HIGH 50%;
#TIMESPEC TS_gtx12_15_clk = PERIOD "gtx12_15_clk" 8ns HIGH 50%;
TIMESPEC TS_gtx16_19_clk = PERIOD "gtx16_19_clk" 8ns HIGH 50%;
NET "gen_phys_bufr[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys_bufr[0]_U_PHY_rx_rec_clk_bufin;
NET "gen_phys_bufr[1].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys_bufr[1]_U_PHY_rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_bufr_0_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys_bufr[0]_U_PHY_rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_bufr_1_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys_bufr[1]_U_PHY_rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
NET "from_phys[0]_rx_clk" TNM = "phy_rx_clocks";
NET "from_phys[1]_rx_clk" TNM = "phy_rx_clocks";
#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_en_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_rst_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_set_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_escr_pps_valid_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
TIMESPEC TS_ignore1 = FROM Ignore_DMTD TIG;
TIMESPEC TS_ignore2 = TO Ignore_DMTD TIG;
TIMESPEC TS_ignore3 = FROM Ignore_sync_ffs TIG;
TIMESPEC TS_ignore4 = TO Ignore_sync_ffs TIG;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_3" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_4" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_5" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_6" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_7" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_8" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_9" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_10" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_11" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_12" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_13" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_14" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_15" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_16" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_17" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_18" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_3" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_4" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_5" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_6" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_7" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_8" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_9" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_10" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_11" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_12" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_13" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_14" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_15" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_16" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_17" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_18" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_3" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_4" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_5" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_6" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_7" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_8" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_9" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_10" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_11" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_12" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_13" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_14" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_15" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_16" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_17" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_18" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_3" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_4" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_5" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_6" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_7" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_8" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_9" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_10" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_11" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_12" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_13" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_14" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_15" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_16" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_17" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_18" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
TIMESPEC TS_ignore8 = FROM "fpga_clk_ref" TO "phy_rx_clocks" 20ns DATAPATHONLY;
TIMESPEC TS_ignore9 = FROM "phy_rx_clocks" TO "fpga_clk_ref" 20ns DATAPATHONLY;
TIMESPEC TS_ignore18 = FROM "fpga_clk_dmtd_p_i" TO "phy_rx_clocks" 20ns DATAPATHONLY;
TIMESPEC TS_ignore19 = FROM "phy_rx_clocks" TO "fpga_clk_dmtd" 20ns DATAPATHONLY;
TIMESPEC TS_ignore38 = FROM "fpga_clk_ref" TO "fpga_clk_dmtd" 20ns DATAPATHONLY;
TIMESPEC TS_ignore39 = FROM "fpga_clk_dmtd" TO "fpga_clk_ref" 20ns DATAPATHONLY;
TIMESPEC TS_ignore40 = FROM "clk_sys" TO "fpga_clk_dmtd" 20ns DATAPATHONLY;
TIMESPEC TS_ignore41 = FROM "fpga_clk_dmtd" TO "clk_sys" 20ns DATAPATHONLY;
TIMESPEC TS_ignore42 = FROM "fpga_clk_ref" TO "clk_sys" 20ns DATAPATHONLY;
TIMESPEC TS_ignore43 = FROM "clk_sys" TO "fpga_clk_ref" 20ns DATAPATHONLY;
TIMESPEC TS_ignore44 = FROM "clk_sys" TO "phy_rx_clocks" 20ns DATAPATHONLY;
TIMESPEC TS_ignore45 = FROM "phy_rx_clocks" TO "clk_sys" 20ns DATAPATHONLY;
TIMESPEC TS_ignore_xclk1 = FROM "fpga_clk_ref" TO "U_swcore_pll_clkout0" 20ns DATAPATHONLY;
TIMESPEC TS_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref" 20ns DATAPATHONLY;
# Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/clk_i_d1" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
AREA_GROUP "pblock_ext_dmtd_2" GROUP=CLOSED;
AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d1" LOC = SLICE_X101Y148;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d0" LOC = SLICE_X101Y148;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d1" AREA_GROUP = "pblock_dmtd_feedback";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d0" AREA_GROUP = "pblock_dmtd_feedback";
AREA_GROUP "pblock_dmtd_feedback" RANGE=SLICE_X38Y154:SLICE_X45Y159;
AREA_GROUP "pblock_dmtd_feedback" RANGE=DSP48_X2Y62:DSP48_X2Y63;
AREA_GROUP "pblock_dmtd_feedback" RANGE=RAMB18_X2Y62:RAMB18_X2Y63;
AREA_GROUP "pblock_dmtd_feedback" RANGE=RAMB36_X2Y31:RAMB36_X2Y31;
AREA_GROUP "pblock_dmtd_feedback" GROUP=CLOSED;
AREA_GROUP "pblock_dmtd_feedback" PLACE=CLOSED;
top/scb_8ports/scb_top_synthesis.vhd
View file @ 72a35829
......@@ -3,10 +3,10 @@
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : scb_top_synthesis.vhd
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk, Hongming
-- Company : CERN BE-CO-HT
-- Created : 2012-03-07
-- Last update: 2014-03-20
-- Last update: 2018-09-07
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -53,6 +53,7 @@ use UNISIM.vcomponents.all;
entity scb_top_synthesis is
generic(
g_cpu_addr_width : integer := 19;
g_with_ext_AD9516: boolean := true;
g_simulation : boolean := false
);
port (
......@@ -70,12 +71,14 @@ entity scb_top_synthesis is
fpga_clk_dmtd_p_i : in std_logic;
fpga_clk_dmtd_n_i : in std_logic;
-- External 10MHz input
--clk_ext_i : in std_logic;
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
clk_sys_dbg_o: out std_logic;
--clk_sys_dbg_o: out std_logic;
-------------------------------------------------------------------------------
-- Atmel EBI bus
......@@ -103,8 +106,9 @@ entity scb_top_synthesis is
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
......@@ -120,7 +124,7 @@ entity scb_top_synthesis is
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -130,7 +134,20 @@ entity scb_top_synthesis is
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- WRS Low Jitter board
-------------------------------------------------------------------------------
ext_clk_62mhz_p_i : in std_logic:='0';
ext_clk_62mhz_n_i : in std_logic:='0';
ext_pll_status_i : in std_logic:='0';
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
-------------------------------------------------------------------------------
-- Clock fanout control
-------------------------------------------------------------------------------
......@@ -153,11 +170,11 @@ entity scb_top_synthesis is
--gtx4_7_clk_n_i : in std_logic;
--gtx4_7_clk_p_i : in std_logic;
gtx8_11_clk_n_i : in std_logic;
gtx8_11_clk_p_i : in std_logic;
--gtx8_11_clk_n_i : in std_logic;
--gtx8_11_clk_p_i : in std_logic;
gtx12_15_clk_n_i : in std_logic;
gtx12_15_clk_p_i : in std_logic;
--gtx12_15_clk_n_i : in std_logic;
--gtx12_15_clk_p_i : in std_logic;
gtx16_19_clk_n_i : in std_logic;
gtx16_19_clk_p_i : in std_logic;
......@@ -168,11 +185,11 @@ entity scb_top_synthesis is
--gtx_txp_o : out std_logic_vector(17 downto 0);
--gtx_txn_o : out std_logic_vector(17 downto 0);
gtx_rxp_i : in std_logic_vector(7 downto 0);
gtx_rxn_i : in std_logic_vector(7 downto 0);
gtx_rxp_i : in std_logic_vector(1 downto 0);
gtx_rxn_i : in std_logic_vector(1 downto 0);
gtx_txp_o : out std_logic_vector(7 downto 0);
gtx_txn_o : out std_logic_vector(7 downto 0);
gtx_txp_o : out std_logic_vector(1 downto 0);
gtx_txn_o : out std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
-- Mini-Backplane signals
......@@ -186,10 +203,10 @@ entity scb_top_synthesis is
sensors_scl_b: inout std_logic;
sensors_sda_b: inout std_logic;
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic;
--mb_fan1_pwm_o : out std_logic;
--mb_fan2_pwm_o : out std_logic;
dbg_clk_ext_o : out std_logic;
-- dbg_clk_ext_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0)
);
......@@ -223,8 +240,8 @@ architecture Behavioral of scb_top_synthesis is
end component;
constant c_NUM_PHYS : integer := 8;
constant c_NUM_PORTS : integer := 8;
constant c_NUM_PHYS : integer := 2;
constant c_NUM_PORTS : integer := 2;
function f_bool2int(x : boolean) return integer is
begin
......@@ -299,12 +316,14 @@ architecture Behavioral of scb_top_synthesis is
attribute buffer_type of clk_aux : signal is "BUFG";
attribute buffer_type of clk_sys : signal is "BUFG";
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal clk_ext_100 : std_logic;
signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic;
signal ext_clk_62mhz, ext_clk_62mhz_bufr : std_logic;
component scb_top_bare
generic (
g_num_ports : integer;
......@@ -323,8 +342,9 @@ architecture Behavioral of scb_top_synthesis is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
......@@ -333,6 +353,7 @@ architecture Behavioral of scb_top_synthesis is
cpu_wb_o : out t_wishbone_slave_out;
cpu_irq_n_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic;
pps_o : out std_logic;
dac_helper_sync_n_o : out std_logic;
dac_helper_sclk_o : out std_logic;
......@@ -340,13 +361,19 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
......@@ -393,7 +420,7 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG3 : std_logic_vector(31 downto 0);
begin
clk_sys_dbg_o <= clk_sys;
--clk_sys_dbg_o <= clk_sys;
--chipscope_icon_1 : chipscope_icon
-- port map (
......@@ -439,25 +466,25 @@ begin
-- IB => gtx4_7_clk_n_i
-- );
U_Clk_Buf_GTX8_11 : IBUFDS_GTXE1
port map
(
O => clk_gtx8_11,
ODIV2 => open,
CEB => '0',
I => gtx8_11_clk_p_i,
IB => gtx8_11_clk_n_i
);
--U_Clk_Buf_GTX8_11 : IBUFDS_GTXE1
-- port map
-- (
-- O => clk_gtx8_11,
-- ODIV2 => open,
-- CEB => '0',
-- I => gtx8_11_clk_p_i,
-- IB => gtx8_11_clk_n_i
-- );
U_Clk_Buf_GTX12_15 : IBUFDS_GTXE1
port map
(
O => clk_gtx12_15,
ODIV2 => open,
CEB => '0',
I => gtx12_15_clk_p_i,
IB => gtx12_15_clk_n_i
);
--U_Clk_Buf_GTX12_15 : IBUFDS_GTXE1
-- port map
-- (
-- O => clk_gtx12_15,
-- ODIV2 => open,
-- CEB => '0',
-- I => gtx12_15_clk_p_i,
-- IB => gtx12_15_clk_n_i
-- );
U_Clk_Buf_GTX16_19 : IBUFDS_GTXE1
port map
......@@ -533,11 +560,36 @@ begin
CLKIN => clk_25mhz);
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
port map (
I => pll_status_i,
O => clk_ext);
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
port map (
I => clk_ext_i,
O => clk_ext);
gen_with_ext_AD9516 : if (g_with_ext_AD9516) generate
U_Buf_ext_clk_62mhz : IBUFGDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => ext_clk_62mhz,
I => ext_clk_62mhz_p_i,
IB => ext_clk_62mhz_n_i);
U_Buf_ext_clk_62mhz_bufr : BUFR
port map (
CE => '1',
CLR => '0',
I => ext_clk_62mhz,
O => ext_clk_62mhz_bufr);
clk_ext_mul <= ext_clk_62mhz_bufr;
clk_ext_mul_locked <= '1'; -- Fixme, connect to ext_pll_status
end generate gen_with_ext_AD9516;
gen_without_ext_AD9516 : if (not g_with_ext_AD9516) generate
U_Ext_PLL1: ext_pll_10_to_100
port map(
......@@ -554,17 +606,18 @@ begin
locked_o => ext_pll_62_locked);
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
dbg_clk_ext_o <= clk_ext_mul;
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
g_width => 1000)
port map(
clk_i => clk_sys,
rst_n_i => sys_rst_n_i,
pulse_i => local_reset,
extended_o => ext_pll_reset);
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
g_width => 1000)
port map(
clk_i => clk_sys,
rst_n_i => sys_rst_n_i,
pulse_i => local_reset,
extended_o => ext_pll_reset);
end generate gen_without_ext_AD9516;
------------------------------------------------
cmp_wb_cpu_bridge : wb_cpu_bridge
......@@ -620,13 +673,13 @@ begin
-------------------------------------------------------------------------------
clk_gtx(1 downto 0) <= (others => clk_gtx16_19);
clk_gtx(5 downto 2) <= (others => clk_gtx12_15);
clk_gtx(7 downto 6) <= (others => clk_gtx8_11);
--clk_gtx(5 downto 2) <= (others => clk_gtx12_15);
--clk_gtx(7 downto 6) <= (others => clk_gtx8_11);
--clk_gtx(11 downto 8) <= (others => clk_gtx8_11);
--clk_gtx(14 downto 12) <= (others => clk_gtx12_15);
--clk_gtx(17 downto 16) <= (others => clk_gtx16_19);
--generate first 4 GTXes with BUFR to reduce the number of global clocks
gen_phys_bufr : for i in 0 to 3 generate
gen_phys_bufr : for i in 0 to 1 generate
U_PHY : wr_gtx_phy_virtex6
generic map (
......@@ -657,36 +710,36 @@ begin
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys_bufr;
gen_phys : for i in 4 to c_NUM_PHYS-1 generate
U_PHY : wr_gtx_phy_virtex6
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
g_use_bufr => false)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys;
--gen_phys : for i in 4 to c_NUM_PHYS-1 generate
-- U_PHY : wr_gtx_phy_virtex6
-- generic map (
-- g_simulation => f_bool2int(g_simulation),
-- g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
-- g_use_bufr => false)
-- port map (
-- clk_gtx_i => clk_gtx(i),
-- clk_ref_i => clk_ref,
-- tx_data_i => to_phys(i).tx_data,
-- tx_k_i => to_phys(i).tx_k,
-- tx_disparity_o => from_phys(i).tx_disparity,
-- tx_enc_err_o => from_phys(i).tx_enc_err,
-- rx_rbclk_o => from_phys(i).rx_clk,
-- rx_data_o => from_phys(i).rx_data,
-- rx_k_o => from_phys(i).rx_k,
-- rx_enc_err_o => from_phys(i).rx_enc_err,
-- rx_bitslide_o => from_phys(i).rx_bitslide,
-- rst_i => to_phys(i).rst,
-- loopen_i => to_phys(i).loopen,
-- pad_txn_o => gtx_txn_o(i),
-- pad_txp_o => gtx_txp_o(i),
-- pad_rxn_i => gtx_rxn_i(i),
-- pad_rxp_i => gtx_rxp_i(i),
-- rdy_o => from_phys(i).rdy);
-- from_phys(i).ref_clk <= clk_ref;
--end generate gen_phys;
gen_terminate_unused_phys : for i in c_NUM_PORTS to c_NUM_PHYS-1 generate
to_phys(i).tx_data <= (others => '0');
......@@ -722,7 +775,8 @@ begin
clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_mul_i => clk_ext_mul,
clk_ext_i => clk_ext,
clk_ext_mul_i => clk_ext_mul,
clk_ext_mul_locked_i=> clk_ext_mul_locked,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
......@@ -731,6 +785,7 @@ begin
cpu_wb_o => top_master_in,
cpu_irq_n_o => cpu_irq_n_o,
pps_i => pps_i,
ppsin_term_o => ppsin_term_o,
pps_o => pps_o,
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
......@@ -738,13 +793,19 @@ begin
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
pll_status_i => clk_ext,
-- pll_status_i => clk_ext,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
......@@ -762,8 +823,8 @@ begin
i2c_sda_oen_o => i2c_sda_oen,
i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in,
mb_fan1_pwm_o => mb_fan1_pwm_o,
mb_fan2_pwm_o => mb_fan2_pwm_o,
--mb_fan1_pwm_o => mb_fan1_pwm_o,
--mb_fan2_pwm_o => mb_fan2_pwm_o,
spll_dbg_o => spll_dbg_o);
i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
......
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