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White Rabbit Switch - Gateware
Commit 6b3c0e71 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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wrsw_rt_subsystem: allow externally sampled RX clocks (DDMTD inside the PHY module)

parent 205a4500
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Showing with 65 additions and 58 deletions
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 6b3c0e71
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-10
-- Last update: 2014-02-06
-- Last update: 2017-06-22
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -47,13 +47,15 @@ entity wrsw_rt_subsystem is
generic (
g_num_rx_clocks : integer;
g_num_ext_clks : integer;
g_simulation : boolean);
g_simulation : boolean;
g_use_sampled_rx_clocks : boolean);
port(
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_rx_sampled_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i : in std_logic;
......@@ -108,7 +110,7 @@ entity wrsw_rt_subsystem is
-- Wired to IODelay in the top module for precise 1-PPS out alignment
-- with clk_aux
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others=>'0');
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others => '0');
ppsdel_tap_o : out std_logic_vector(4 downto 0);
ppsdel_tap_wr_o : out std_logic;
......@@ -162,6 +164,7 @@ architecture rtl of wrsw_rt_subsystem is
g_reverse_dmtds : boolean;
g_ref_clock_rate : integer;
g_ext_clock_rate : integer;
g_use_sampled_ref_clocks : boolean;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
......@@ -171,6 +174,7 @@ architecture rtl of wrsw_rt_subsystem is
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_ref_sampled_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic;
......@@ -254,7 +258,7 @@ architecture rtl of wrsw_rt_subsystem is
signal dac_out_data, dac_dmtd_data : std_logic_vector(15 downto 0);
signal dac_out_load, dac_dmtd_load : std_logic;
signal clk_rx_vec : std_logic_vector(g_num_rx_clocks-1 downto 0);
signal clk_rx_vec, clk_rx_sampled_vec : std_logic_vector(g_num_rx_clocks-1 downto 0);
signal pps_csync : std_logic;
signal pps_valid : std_logic;
......@@ -278,6 +282,7 @@ architecture rtl of wrsw_rt_subsystem is
begin -- rtl
clk_rx_vec(g_num_rx_clocks-1 downto 0) <= clk_rx_i;
clk_rx_sampled_vec(g_num_rx_clocks-1 downto 0) <= clk_rx_sampled_i;
cnx_slave_in(c_MASTER_CPU) <= wb_i;
wb_o <= cnx_slave_out(c_MASTER_CPU);
......@@ -354,13 +359,15 @@ begin -- rtl
g_divide_input_by_2 => false,
g_with_debug_fifo => true,
g_ref_clock_rate => 62500000,
g_ext_clock_rate => 10000000)
g_ext_clock_rate => 10000000,
g_use_sampled_ref_clocks => g_use_sampled_rx_clocks)
port map (
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
rst_ref_n_i => rst_ref_n_i,
rst_ext_n_i => rst_ext_n_i,
rst_dmtd_n_i => rst_dmtd_n_i,
clk_ref_sampled_i => clk_rx_sampled_vec,
clk_ref_i => clk_rx_vec,
clk_fb_i(0) => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
......@@ -477,7 +484,7 @@ begin -- rtl
slave_o => cnx_master_in(c_SLAVE_TIMER),
desc_o => open);
U_GEN_10_MHZ: xwrsw_gen_10mhz
U_GEN_10_MHZ : xwrsw_gen_10mhz
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
......
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