Commit 15398ab3 authored by Harvey Leicester's avatar Harvey Leicester

removed unused tcl scripts

parent 1343cd54
################################################################
# This is a generated script based on design: top
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2018.2
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source top_script.tcl
# The design that will be created by this Tcl script contains the following
# module references:
# afcz_wrs_8p_top
# Please add the sources of those modules before sourcing this Tcl script.
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu7ev-ffvf1517-2-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name top
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:zynq_ultra_ps_e:3.2\
xilinx.com:ip:ila:6.2\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
##################################################################
# CHECK Modules
##################################################################
set bCheckModules 1
if { $bCheckModules == 1 } {
set list_check_mods "\
afcz_wrs_8p_top\
"
set list_mods_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
foreach mod_vlnv $list_check_mods {
if { [can_resolve_reference $mod_vlnv] == 0 } {
lappend list_mods_missing $mod_vlnv
}
}
if { $list_mods_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
# Create ports
set MMC_nreset_i [ create_bd_port -dir I MMC_nreset_i ]
set clk_20m_vcxo1_i [ create_bd_port -dir I clk_20m_vcxo1_i ]
set i2c_scl_b [ create_bd_port -dir IO i2c_scl_b ]
set i2c_sda_b [ create_bd_port -dir IO i2c_sda_b ]
set mgt227_rx_n_i [ create_bd_port -dir I -from 3 -to 0 mgt227_rx_n_i ]
set mgt227_rx_p_i [ create_bd_port -dir I -from 3 -to 0 mgt227_rx_p_i ]
set mgt227_tx_n_o [ create_bd_port -dir O -from 3 -to 0 mgt227_tx_n_o ]
set mgt227_tx_p_o [ create_bd_port -dir O -from 3 -to 0 mgt227_tx_p_o ]
set mgt228_rx_n_i [ create_bd_port -dir I -from 3 -to 0 mgt228_rx_n_i ]
set mgt228_rx_p_i [ create_bd_port -dir I -from 3 -to 0 mgt228_rx_p_i ]
set mgt228_tx_n_o [ create_bd_port -dir O -from 3 -to 0 mgt228_tx_n_o ]
set mgt228_tx_p_o [ create_bd_port -dir O -from 3 -to 0 mgt228_tx_p_o ]
set mgtclk1_224_n_i [ create_bd_port -dir I mgtclk1_224_n_i ]
set mgtclk1_224_p_i [ create_bd_port -dir I mgtclk1_224_p_i ]
set si57x_scl_b [ create_bd_port -dir IO si57x_scl_b ]
set si57x_sda_b [ create_bd_port -dir IO si57x_sda_b ]
set uart_rxd_i [ create_bd_port -dir I uart_rxd_i ]
set uart_txd_o [ create_bd_port -dir O uart_txd_o ]
set wr_dac1_din_o [ create_bd_port -dir O wr_dac1_din_o ]
set wr_dac1_sclk_o [ create_bd_port -dir O wr_dac1_sclk_o ]
set wr_dac1_sync_n_o [ create_bd_port -dir O -from 1 -to 0 wr_dac1_sync_n_o ]
# Create instance: afcz_wrs_8p_top_0, and set properties
set block_name afcz_wrs_8p_top
set block_cell_name afcz_wrs_8p_top_0
if { [catch {set afcz_wrs_8p_top_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $afcz_wrs_8p_top_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.ENABLE_ADVANCED_OPTIONS {1} \
CONFIG.NUM_MI {1} \
CONFIG.XBAR_DATA_WIDTH {32} \
] $axi_interconnect_0
# Create instance: cmp_proc_sys_reset, and set properties
set cmp_proc_sys_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 cmp_proc_sys_reset ]
set_property -dict [ list \
CONFIG.C_AUX_RESET_HIGH {0} \
CONFIG.C_AUX_RST_WIDTH {1} \
CONFIG.C_EXT_RST_WIDTH {1} \
] $cmp_proc_sys_reset
# Create instance: cmp_zynq, and set properties
set cmp_zynq [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.2 cmp_zynq ]
set_property -dict [ list \
CONFIG.CAN0_BOARD_INTERFACE {custom} \
CONFIG.CAN1_BOARD_INTERFACE {custom} \
CONFIG.CSU_BOARD_INTERFACE {custom} \
CONFIG.DP_BOARD_INTERFACE {custom} \
CONFIG.GEM0_BOARD_INTERFACE {custom} \
CONFIG.GEM1_BOARD_INTERFACE {custom} \
CONFIG.GEM2_BOARD_INTERFACE {custom} \
CONFIG.GEM3_BOARD_INTERFACE {custom} \
CONFIG.GPIO_BOARD_INTERFACE {custom} \
CONFIG.IIC0_BOARD_INTERFACE {custom} \
CONFIG.IIC1_BOARD_INTERFACE {custom} \
CONFIG.NAND_BOARD_INTERFACE {custom} \
CONFIG.PCIE_BOARD_INTERFACE {custom} \
CONFIG.PJTAG_BOARD_INTERFACE {custom} \
CONFIG.PMU_BOARD_INTERFACE {custom} \
CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
CONFIG.PSU_MIO_0_DIRECTION {out} \
CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_0_SLEW {slow} \
CONFIG.PSU_MIO_10_DIRECTION {inout} \
CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_10_SLEW {slow} \
CONFIG.PSU_MIO_11_DIRECTION {inout} \
CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_11_SLEW {slow} \
CONFIG.PSU_MIO_12_DIRECTION {inout} \
CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_12_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_12_SLEW {slow} \
CONFIG.PSU_MIO_13_DIRECTION {inout} \
CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_13_SLEW {slow} \
CONFIG.PSU_MIO_14_DIRECTION {inout} \
CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_14_SLEW {slow} \
CONFIG.PSU_MIO_15_DIRECTION {inout} \
CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_15_SLEW {slow} \
CONFIG.PSU_MIO_16_DIRECTION {inout} \
CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_16_SLEW {slow} \
CONFIG.PSU_MIO_17_DIRECTION {inout} \
CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_17_SLEW {slow} \
CONFIG.PSU_MIO_18_DIRECTION {in} \
CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_18_SLEW {slow} \
CONFIG.PSU_MIO_19_DIRECTION {out} \
CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_19_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_19_SLEW {slow} \
CONFIG.PSU_MIO_1_DIRECTION {inout} \
CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_1_SLEW {slow} \
CONFIG.PSU_MIO_20_DIRECTION {out} \
CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_20_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_20_SLEW {slow} \
CONFIG.PSU_MIO_21_DIRECTION {in} \
CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_21_SLEW {slow} \
CONFIG.PSU_MIO_22_DIRECTION {inout} \
CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_22_SLEW {slow} \
CONFIG.PSU_MIO_23_DIRECTION {inout} \
CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_23_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_23_SLEW {slow} \
CONFIG.PSU_MIO_24_DIRECTION {out} \
CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_24_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_24_SLEW {slow} \
CONFIG.PSU_MIO_25_DIRECTION {in} \
CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_25_SLEW {slow} \
CONFIG.PSU_MIO_26_DIRECTION {out} \
CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_26_SLEW {slow} \
CONFIG.PSU_MIO_27_DIRECTION {out} \
CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_27_SLEW {slow} \
CONFIG.PSU_MIO_28_DIRECTION {out} \
CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_28_SLEW {slow} \
CONFIG.PSU_MIO_29_DIRECTION {out} \
CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_29_SLEW {slow} \
CONFIG.PSU_MIO_2_DIRECTION {inout} \
CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_2_SLEW {slow} \
CONFIG.PSU_MIO_30_DIRECTION {out} \
CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_30_SLEW {slow} \
CONFIG.PSU_MIO_31_DIRECTION {out} \
CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_31_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_31_SLEW {slow} \
CONFIG.PSU_MIO_32_DIRECTION {in} \
CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_32_SLEW {slow} \
CONFIG.PSU_MIO_33_DIRECTION {in} \
CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_33_SLEW {slow} \
CONFIG.PSU_MIO_34_DIRECTION {in} \
CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_34_SLEW {slow} \
CONFIG.PSU_MIO_35_DIRECTION {in} \
CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_35_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_35_SLEW {slow} \
CONFIG.PSU_MIO_36_DIRECTION {in} \
CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_36_SLEW {slow} \
CONFIG.PSU_MIO_37_DIRECTION {in} \
CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_37_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_37_SLEW {slow} \
CONFIG.PSU_MIO_38_DIRECTION {inout} \
CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_38_SLEW {slow} \
CONFIG.PSU_MIO_39_DIRECTION {inout} \
CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_39_SLEW {slow} \
CONFIG.PSU_MIO_3_DIRECTION {inout} \
CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_3_SLEW {slow} \
CONFIG.PSU_MIO_40_DIRECTION {inout} \
CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_40_SLEW {slow} \
CONFIG.PSU_MIO_41_DIRECTION {inout} \
CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_41_SLEW {slow} \
CONFIG.PSU_MIO_42_DIRECTION {inout} \
CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_42_SLEW {slow} \
CONFIG.PSU_MIO_43_DIRECTION {out} \
CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_43_SLEW {slow} \
CONFIG.PSU_MIO_44_DIRECTION {in} \
CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_44_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_44_SLEW {slow} \
CONFIG.PSU_MIO_45_DIRECTION {in} \
CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_45_SLEW {slow} \
CONFIG.PSU_MIO_46_DIRECTION {inout} \
CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_46_SLEW {slow} \
CONFIG.PSU_MIO_47_DIRECTION {inout} \
CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_47_SLEW {slow} \
CONFIG.PSU_MIO_48_DIRECTION {inout} \
CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_48_SLEW {slow} \
CONFIG.PSU_MIO_49_DIRECTION {inout} \
CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_49_SLEW {slow} \
CONFIG.PSU_MIO_4_DIRECTION {inout} \
CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_4_SLEW {slow} \
CONFIG.PSU_MIO_50_DIRECTION {inout} \
CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_50_SLEW {slow} \
CONFIG.PSU_MIO_51_DIRECTION {out} \
CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_51_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_51_SLEW {slow} \
CONFIG.PSU_MIO_52_DIRECTION {in} \
CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_52_SLEW {slow} \
CONFIG.PSU_MIO_53_DIRECTION {in} \
CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_53_SLEW {slow} \
CONFIG.PSU_MIO_54_DIRECTION {inout} \
CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_54_SLEW {slow} \
CONFIG.PSU_MIO_55_DIRECTION {in} \
CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_55_SLEW {slow} \
CONFIG.PSU_MIO_56_DIRECTION {inout} \
CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_56_SLEW {slow} \
CONFIG.PSU_MIO_57_DIRECTION {inout} \
CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_57_SLEW {slow} \
CONFIG.PSU_MIO_58_DIRECTION {out} \
CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_58_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_58_SLEW {slow} \
CONFIG.PSU_MIO_59_DIRECTION {inout} \
CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_59_SLEW {slow} \
CONFIG.PSU_MIO_5_DIRECTION {out} \
CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_5_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_5_SLEW {slow} \
CONFIG.PSU_MIO_60_DIRECTION {inout} \
CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_60_SLEW {slow} \
CONFIG.PSU_MIO_61_DIRECTION {inout} \
CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_61_SLEW {slow} \
CONFIG.PSU_MIO_62_DIRECTION {inout} \
CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_62_SLEW {slow} \
CONFIG.PSU_MIO_63_DIRECTION {inout} \
CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_63_SLEW {slow} \
CONFIG.PSU_MIO_64_DIRECTION {out} \
CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_64_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_64_SLEW {fast} \
CONFIG.PSU_MIO_65_DIRECTION {out} \
CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_65_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_65_SLEW {fast} \
CONFIG.PSU_MIO_66_DIRECTION {out} \
CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_66_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_66_SLEW {fast} \
CONFIG.PSU_MIO_67_DIRECTION {out} \
CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_67_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_67_SLEW {fast} \
CONFIG.PSU_MIO_68_DIRECTION {out} \
CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_68_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_68_SLEW {fast} \
CONFIG.PSU_MIO_69_DIRECTION {out} \
CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_69_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_69_SLEW {fast} \
CONFIG.PSU_MIO_6_DIRECTION {out} \
CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_6_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_6_SLEW {slow} \
CONFIG.PSU_MIO_70_DIRECTION {in} \
CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_70_PULLUPDOWN {pulldown} \
CONFIG.PSU_MIO_70_SLEW {slow} \
CONFIG.PSU_MIO_71_DIRECTION {in} \
CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_71_PULLUPDOWN {pulldown} \
CONFIG.PSU_MIO_71_SLEW {slow} \
CONFIG.PSU_MIO_72_DIRECTION {in} \
CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_72_PULLUPDOWN {pulldown} \
CONFIG.PSU_MIO_72_SLEW {slow} \
CONFIG.PSU_MIO_73_DIRECTION {in} \
CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_73_PULLUPDOWN {pulldown} \
CONFIG.PSU_MIO_73_SLEW {slow} \
CONFIG.PSU_MIO_74_DIRECTION {in} \
CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_74_PULLUPDOWN {pulldown} \
CONFIG.PSU_MIO_74_SLEW {slow} \
CONFIG.PSU_MIO_75_DIRECTION {in} \
CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_75_PULLUPDOWN {pulldown} \
CONFIG.PSU_MIO_75_SLEW {slow} \
CONFIG.PSU_MIO_76_DIRECTION {out} \
CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_76_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_76_SLEW {slow} \
CONFIG.PSU_MIO_77_DIRECTION {inout} \
CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_77_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_77_SLEW {slow} \
CONFIG.PSU_MIO_7_DIRECTION {inout} \
CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_7_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_7_SLEW {slow} \
CONFIG.PSU_MIO_8_DIRECTION {inout} \
CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_8_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_8_SLEW {slow} \
CONFIG.PSU_MIO_9_DIRECTION {inout} \
CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_9_SLEW {slow} \
CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk########I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#######Gem 0#Gem 0#Gem 0#Gem 0#Gem 0#Gem 0#Gem 0#Gem 0#Gem 0#Gem 0#Gem 0#Gem 0##SD 1#SD 1#SD 1#SD 1##SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#############MDIO 0#MDIO 0} \
CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk########scl_out#sda_out#scl_out#sda_out#rxd#txd#######rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl##sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]##sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#############gem0_mdc#gem0_mdio_out} \
CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \
CONFIG.PSU_SMC_CYCLE_T0 {NA} \
CONFIG.PSU_SMC_CYCLE_T1 {NA} \
CONFIG.PSU_SMC_CYCLE_T2 {NA} \
CONFIG.PSU_SMC_CYCLE_T3 {NA} \
CONFIG.PSU_SMC_CYCLE_T4 {NA} \
CONFIG.PSU_SMC_CYCLE_T5 {NA} \
CONFIG.PSU_SMC_CYCLE_T6 {NA} \
CONFIG.PSU_VALUE_SILVERSION {3} \
CONFIG.PSU__ACPU0__POWER__ON {1} \
CONFIG.PSU__ACPU1__POWER__ON {1} \
CONFIG.PSU__ACPU2__POWER__ON {1} \
CONFIG.PSU__ACPU3__POWER__ON {1} \
CONFIG.PSU__ACTUAL__IP {1} \
CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
CONFIG.PSU__AFI0_COHERENCY {0} \
CONFIG.PSU__AFI1_COHERENCY {0} \
CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {48} \
CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1200} \
CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {42} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {63} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.667} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {10} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {320} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {320} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {248.000} \
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250} \
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {60} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724138} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {52} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {99.200} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125.000000} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {60} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {62.500000} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {24} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {62.5} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {56} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {200.000000} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {7} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
CONFIG.PSU__CSU_COHERENCY {0} \
CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
CONFIG.PSU__DDRC__AL {0} \
CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
CONFIG.PSU__DDRC__CL {16} \
CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
CONFIG.PSU__DDRC__COMPONENTS {Components} \
CONFIG.PSU__DDRC__CWL {14} \
CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
CONFIG.PSU__DDRC__ECC {Disabled} \
CONFIG.PSU__DDRC__ECC_SCRUB {0} \
CONFIG.PSU__DDRC__ENABLE {1} \
CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
CONFIG.PSU__DDRC__FGRM {1X} \
CONFIG.PSU__DDRC__FREQ_MHZ {1} \
CONFIG.PSU__DDRC__LP_ASR {manual normal} \
CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
CONFIG.PSU__DDRC__PLL_BYPASS {0} \
CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400P} \
CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
CONFIG.PSU__DDRC__T_FAW {30.0} \
CONFIG.PSU__DDRC__T_RAS_MIN {32} \
CONFIG.PSU__DDRC__T_RC {45.32} \
CONFIG.PSU__DDRC__T_RCD {16} \
CONFIG.PSU__DDRC__T_RP {16} \
CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
CONFIG.PSU__DDRC__VREF {1} \
CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
CONFIG.PSU__DDR_QOS_ENABLE {0} \
CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \
CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \
CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \
CONFIG.PSU__DDR__INTERFACE__FREQMHZ {600.000} \
CONFIG.PSU__DEVICE_TYPE {EV} \
CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {0} \
CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \
CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__DLL__ISUSED {1} \
CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
CONFIG.PSU__ENET0__FIFO__ENABLE {0} \
CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {1} \
CONFIG.PSU__ENET0__GRP_MDIO__IO {MIO 76 .. 77} \
CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__ENET0__PERIPHERAL__IO {MIO 26 .. 37} \
CONFIG.PSU__ENET0__PTP__ENABLE {0} \
CONFIG.PSU__ENET0__TSU__ENABLE {0} \
CONFIG.PSU__ENET1__FIFO__ENABLE {0} \
CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \
CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__ENET1__PTP__ENABLE {0} \
CONFIG.PSU__ENET1__TSU__ENABLE {0} \
CONFIG.PSU__ENET2__FIFO__ENABLE {0} \
CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \
CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__ENET2__PTP__ENABLE {0} \
CONFIG.PSU__ENET2__TSU__ENABLE {0} \
CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
CONFIG.PSU__ENET3__GRP_MDIO__IO {<Select>} \
CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__ENET3__PERIPHERAL__IO {<Select>} \
CONFIG.PSU__ENET3__PTP__ENABLE {0} \
CONFIG.PSU__ENET3__TSU__ENABLE {0} \
CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
CONFIG.PSU__EN_EMIO_TRACE {0} \
CONFIG.PSU__EP__IP {0} \
CONFIG.PSU__EXPAND__CORESIGHT {0} \
CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
CONFIG.PSU__EXPAND__GIC {0} \
CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
CONFIG.PSU__FPGA_PL0_ENABLE {1} \
CONFIG.PSU__FPGA_PL1_ENABLE {0} \
CONFIG.PSU__FPGA_PL2_ENABLE {0} \
CONFIG.PSU__FPGA_PL3_ENABLE {0} \
CONFIG.PSU__FP__POWER__ON {1} \
CONFIG.PSU__FTM__CTI_IN_0 {0} \
CONFIG.PSU__FTM__CTI_IN_1 {0} \
CONFIG.PSU__FTM__CTI_IN_2 {0} \
CONFIG.PSU__FTM__CTI_IN_3 {0} \
CONFIG.PSU__FTM__CTI_OUT_0 {0} \
CONFIG.PSU__FTM__CTI_OUT_1 {0} \
CONFIG.PSU__FTM__CTI_OUT_2 {0} \
CONFIG.PSU__FTM__CTI_OUT_3 {0} \
CONFIG.PSU__FTM__GPI {0} \
CONFIG.PSU__FTM__GPO {0} \
CONFIG.PSU__GEM0_COHERENCY {0} \
CONFIG.PSU__GEM1_COHERENCY {0} \
CONFIG.PSU__GEM2_COHERENCY {0} \
CONFIG.PSU__GEM3_COHERENCY {0} \
CONFIG.PSU__GEM__TSU__ENABLE {0} \
CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__GPIO_EMIO_WIDTH {1} \
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
CONFIG.PSU__GPU_PP0__POWER__ON {1} \
CONFIG.PSU__GPU_PP1__POWER__ON {1} \
CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
CONFIG.PSU__GT__PRE_EMPH_LVL_4 {} \
CONFIG.PSU__GT__VLT_SWNG_LVL_4 {} \
CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \
CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \
CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \
CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \
CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \
CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
CONFIG.PSU__L2_BANK0__POWER__ON {1} \
CONFIG.PSU__LPDMA0_COHERENCY {0} \
CONFIG.PSU__LPDMA1_COHERENCY {0} \
CONFIG.PSU__LPDMA2_COHERENCY {0} \
CONFIG.PSU__LPDMA3_COHERENCY {0} \
CONFIG.PSU__LPDMA4_COHERENCY {0} \
CONFIG.PSU__LPDMA5_COHERENCY {0} \
CONFIG.PSU__LPDMA6_COHERENCY {0} \
CONFIG.PSU__LPDMA7_COHERENCY {0} \
CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
CONFIG.PSU__MAXIGP0__DATA_WIDTH {32} \
CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
CONFIG.PSU__NAND_COHERENCY {0} \
CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \
CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \
CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \
CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \
CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
CONFIG.PSU__NUM_FABRIC_RESETS {1} \
CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
CONFIG.PSU__PCIE__ACS_VIOLATION {0} \
CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \
CONFIG.PSU__PCIE__BAR0_64BIT {0} \
CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR0_VAL {} \
CONFIG.PSU__PCIE__BAR1_64BIT {0} \
CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR1_VAL {} \
CONFIG.PSU__PCIE__BAR2_64BIT {0} \
CONFIG.PSU__PCIE__BAR2_ENABLE {0} \
CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR2_VAL {} \
CONFIG.PSU__PCIE__BAR3_64BIT {0} \
CONFIG.PSU__PCIE__BAR3_ENABLE {0} \
CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR3_VAL {} \
CONFIG.PSU__PCIE__BAR4_64BIT {0} \
CONFIG.PSU__PCIE__BAR4_ENABLE {0} \
CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR4_VAL {} \
CONFIG.PSU__PCIE__BAR5_64BIT {0} \
CONFIG.PSU__PCIE__BAR5_ENABLE {0} \
CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR5_VAL {} \
CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \
CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \
CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \
CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \
CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \
CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \
CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \
CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \
CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \
CONFIG.PSU__PCIE__ECRC_CHECK {0} \
CONFIG.PSU__PCIE__ECRC_ERR {0} \
CONFIG.PSU__PCIE__ECRC_GEN {0} \
CONFIG.PSU__PCIE__EROM_ENABLE {0} \
CONFIG.PSU__PCIE__EROM_VAL {} \
CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \
CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \
CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \
CONFIG.PSU__PCIE__INTX_GENERATION {0} \
CONFIG.PSU__PCIE__LANE0__ENABLE {0} \
CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \
CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \
CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \
CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \
CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \
CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \
CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \
CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
CONFIG.PSU__PCIE__MULTIHEADER {0} \
CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \
CONFIG.PSU__PCIE__RECEIVER_ERR {0} \
CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \
CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
CONFIG.PSU__PCIE__REVISION_ID {0x0} \
CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \
CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \
CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \
CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \
CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \
CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \
CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__PL_CLK0_BUF {TRUE} \
CONFIG.PSU__PL_CLK1_BUF {FALSE} \
CONFIG.PSU__PL_CLK2_BUF {FALSE} \
CONFIG.PSU__PL_CLK3_BUF {FALSE} \
CONFIG.PSU__PL__POWER__ON {1} \
CONFIG.PSU__PMU_COHERENCY {0} \
CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
CONFIG.PSU__PMU__GPI0__ENABLE {0} \
CONFIG.PSU__PMU__GPI1__ENABLE {0} \
CONFIG.PSU__PMU__GPI2__ENABLE {0} \
CONFIG.PSU__PMU__GPI3__ENABLE {0} \
CONFIG.PSU__PMU__GPI4__ENABLE {0} \
CONFIG.PSU__PMU__GPI5__ENABLE {0} \
CONFIG.PSU__PMU__GPO0__ENABLE {0} \
CONFIG.PSU__PMU__GPO1__ENABLE {0} \
CONFIG.PSU__PMU__GPO2__ENABLE {0} \
CONFIG.PSU__PMU__GPO3__ENABLE {0} \
CONFIG.PSU__PMU__GPO4__ENABLE {0} \
CONFIG.PSU__PMU__GPO5__ENABLE {0} \
CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
CONFIG.PSU__PRESET_APPLIED {0} \
CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
CONFIG.PSU__PROTECTION__DEBUG {0} \
CONFIG.PSU__PROTECTION__ENABLE {0} \
CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD000000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD020000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD040000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD610000 ;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \
CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \
CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;1|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \
CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|FPD;RCPU_GIC;F9000000;F900FFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;1|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9000000;F907FFFF;1} \
CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU} \
CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
CONFIG.PSU__PSS_REF_CLK__FREQMHZ {50} \
CONFIG.PSU__QSPI_COHERENCY {0} \
CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
CONFIG.PSU__REPORT__DBGLOG {0} \
CONFIG.PSU__RPU_COHERENCY {0} \
CONFIG.PSU__RPU__POWER__ON {1} \
CONFIG.PSU__SATA__LANE0__ENABLE {0} \
CONFIG.PSU__SATA__LANE0__IO {<Select>} \
CONFIG.PSU__SATA__LANE1__ENABLE {0} \
CONFIG.PSU__SATA__LANE1__IO {<Select>} \
CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__SATA__REF_CLK_FREQ {<Select>} \
CONFIG.PSU__SATA__REF_CLK_SEL {<Select>} \
CONFIG.PSU__SD0_COHERENCY {0} \
CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \
CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__SD0__RESET__ENABLE {0} \
CONFIG.PSU__SD1_COHERENCY {0} \
CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \
CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \
CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \
CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \
CONFIG.PSU__SD1__RESET__ENABLE {0} \
CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \
CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \
CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \
CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
CONFIG.PSU__TCM0A__POWER__ON {1} \
CONFIG.PSU__TCM0B__POWER__ON {1} \
CONFIG.PSU__TCM1A__POWER__ON {1} \
CONFIG.PSU__TCM1B__POWER__ON {1} \
CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__TRISTATE__INVERTED {1} \
CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
CONFIG.PSU__UART0__BAUD_RATE {115200} \
CONFIG.PSU__UART0__MODEM__ENABLE {0} \
CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
CONFIG.PSU__UART1__BAUD_RATE {115200} \
CONFIG.PSU__UART1__MODEM__ENABLE {0} \
CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__UART1__PERIPHERAL__IO {EMIO} \
CONFIG.PSU__USB0_COHERENCY {0} \
CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
CONFIG.PSU__USB1_COHERENCY {0} \
CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane1} \
CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__USE__ADMA {0} \
CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
CONFIG.PSU__USE__AUDIO {0} \
CONFIG.PSU__USE__CLK {0} \
CONFIG.PSU__USE__CLK0 {0} \
CONFIG.PSU__USE__CLK1 {0} \
CONFIG.PSU__USE__CLK2 {0} \
CONFIG.PSU__USE__CLK3 {0} \
CONFIG.PSU__USE__CROSS_TRIGGER {0} \
CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
CONFIG.PSU__USE__DEBUG__TEST {0} \
CONFIG.PSU__USE__EVENT_RPU {0} \
CONFIG.PSU__USE__FABRIC__RST {1} \
CONFIG.PSU__USE__FTM {0} \
CONFIG.PSU__USE__GDMA {0} \
CONFIG.PSU__USE__IRQ {0} \
CONFIG.PSU__USE__IRQ0 {1} \
CONFIG.PSU__USE__IRQ1 {0} \
CONFIG.PSU__USE__M_AXI_GP0 {1} \
CONFIG.PSU__USE__M_AXI_GP1 {0} \
CONFIG.PSU__USE__M_AXI_GP2 {0} \
CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
CONFIG.PSU__USE__RST0 {0} \
CONFIG.PSU__USE__RST1 {0} \
CONFIG.PSU__USE__RST2 {0} \
CONFIG.PSU__USE__RST3 {0} \
CONFIG.PSU__USE__RTC {0} \
CONFIG.PSU__USE__STM {0} \
CONFIG.PSU__USE__S_AXI_ACE {0} \
CONFIG.PSU__USE__S_AXI_ACP {0} \
CONFIG.PSU__USE__S_AXI_GP0 {0} \
CONFIG.PSU__USE__S_AXI_GP1 {0} \
CONFIG.PSU__USE__S_AXI_GP2 {0} \
CONFIG.PSU__USE__S_AXI_GP3 {0} \
CONFIG.PSU__USE__S_AXI_GP4 {0} \
CONFIG.PSU__USE__S_AXI_GP5 {0} \
CONFIG.PSU__USE__S_AXI_GP6 {0} \
CONFIG.PSU__USE__VIDEO {0} \
CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
CONFIG.QSPI_BOARD_INTERFACE {custom} \
CONFIG.SATA_BOARD_INTERFACE {custom} \
CONFIG.SD0_BOARD_INTERFACE {custom} \
CONFIG.SD1_BOARD_INTERFACE {custom} \
CONFIG.SPI0_BOARD_INTERFACE {custom} \
CONFIG.SPI1_BOARD_INTERFACE {custom} \
CONFIG.SUBPRESET1 {Custom} \
CONFIG.SUBPRESET2 {Custom} \
CONFIG.SWDT0_BOARD_INTERFACE {custom} \
CONFIG.SWDT1_BOARD_INTERFACE {custom} \
CONFIG.TRACE_BOARD_INTERFACE {custom} \
CONFIG.TTC0_BOARD_INTERFACE {custom} \
CONFIG.TTC1_BOARD_INTERFACE {custom} \
CONFIG.TTC2_BOARD_INTERFACE {custom} \
CONFIG.TTC3_BOARD_INTERFACE {custom} \
CONFIG.UART0_BOARD_INTERFACE {custom} \
CONFIG.UART1_BOARD_INTERFACE {custom} \
CONFIG.USB0_BOARD_INTERFACE {custom} \
CONFIG.USB1_BOARD_INTERFACE {custom} \
] $cmp_zynq
# Create instance: ila_0, and set properties
set ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.2 ila_0 ]
set_property -dict [ list \
CONFIG.ALL_PROBE_SAME_MU_CNT {2} \
CONFIG.C_ADV_TRIGGER {true} \
CONFIG.C_EN_STRG_QUAL {1} \
CONFIG.C_PROBE0_MU_CNT {2} \
CONFIG.C_PROBE10_MU_CNT {2} \
CONFIG.C_PROBE11_MU_CNT {2} \
CONFIG.C_PROBE12_MU_CNT {2} \
CONFIG.C_PROBE13_MU_CNT {2} \
CONFIG.C_PROBE14_MU_CNT {2} \
CONFIG.C_PROBE15_MU_CNT {2} \
CONFIG.C_PROBE16_MU_CNT {2} \
CONFIG.C_PROBE17_MU_CNT {2} \
CONFIG.C_PROBE18_MU_CNT {2} \
CONFIG.C_PROBE19_MU_CNT {2} \
CONFIG.C_PROBE1_MU_CNT {2} \
CONFIG.C_PROBE20_MU_CNT {2} \
CONFIG.C_PROBE21_MU_CNT {2} \
CONFIG.C_PROBE22_MU_CNT {2} \
CONFIG.C_PROBE23_MU_CNT {2} \
CONFIG.C_PROBE24_MU_CNT {2} \
CONFIG.C_PROBE25_MU_CNT {2} \
CONFIG.C_PROBE26_MU_CNT {2} \
CONFIG.C_PROBE27_MU_CNT {2} \
CONFIG.C_PROBE28_MU_CNT {2} \
CONFIG.C_PROBE29_MU_CNT {2} \
CONFIG.C_PROBE2_MU_CNT {2} \
CONFIG.C_PROBE30_MU_CNT {2} \
CONFIG.C_PROBE31_MU_CNT {2} \
CONFIG.C_PROBE32_MU_CNT {2} \
CONFIG.C_PROBE33_MU_CNT {2} \
CONFIG.C_PROBE34_MU_CNT {2} \
CONFIG.C_PROBE35_MU_CNT {2} \
CONFIG.C_PROBE36_MU_CNT {2} \
CONFIG.C_PROBE37_MU_CNT {2} \
CONFIG.C_PROBE38_MU_CNT {2} \
CONFIG.C_PROBE39_MU_CNT {2} \
CONFIG.C_PROBE3_MU_CNT {2} \
CONFIG.C_PROBE40_MU_CNT {2} \
CONFIG.C_PROBE41_MU_CNT {2} \
CONFIG.C_PROBE42_MU_CNT {2} \
CONFIG.C_PROBE43_MU_CNT {2} \
CONFIG.C_PROBE4_MU_CNT {2} \
CONFIG.C_PROBE5_MU_CNT {2} \
CONFIG.C_PROBE6_MU_CNT {2} \
CONFIG.C_PROBE7_MU_CNT {2} \
CONFIG.C_PROBE8_MU_CNT {2} \
CONFIG.C_PROBE9_MU_CNT {2} \
] $ila_0
# Create instance: ila_1, and set properties
set ila_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.2 ila_1 ]
# Create interface connections
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins afcz_wrs_8p_top_0/axi4l] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net -intf_net [get_bd_intf_nets axi_interconnect_0_M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins ila_0/SLOT_0_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins cmp_zynq/M_AXI_HPM0_FPD]
connect_bd_intf_net -intf_net [get_bd_intf_nets smartconnect_0_M00_AXI] [get_bd_intf_pins cmp_zynq/M_AXI_HPM0_FPD] [get_bd_intf_pins ila_1/SLOT_0_AXI]
# Create port connections
connect_bd_net -net M00_ACLK_1 [get_bd_pins afcz_wrs_8p_top_0/axi4l_aclk] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins ila_0/clk]
connect_bd_net -net Net [get_bd_ports i2c_scl_b] [get_bd_pins afcz_wrs_8p_top_0/afcz_scl_b]
connect_bd_net -net Net1 [get_bd_ports i2c_sda_b] [get_bd_pins afcz_wrs_8p_top_0/afcz_sda_b]
connect_bd_net -net Net2 [get_bd_ports si57x_scl_b] [get_bd_pins afcz_wrs_8p_top_0/si57x_scl_b]
connect_bd_net -net Net3 [get_bd_ports si57x_sda_b] [get_bd_pins afcz_wrs_8p_top_0/si57x_sda_b]
connect_bd_net -net afcz_wrs_8p_top_0_axi4l_aresetn [get_bd_pins afcz_wrs_8p_top_0/axi4l_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN]
connect_bd_net -net afcz_wrs_8p_top_0_mgt227_tx_n_o [get_bd_ports mgt227_tx_n_o] [get_bd_pins afcz_wrs_8p_top_0/mgt227_tx_n_o]
connect_bd_net -net afcz_wrs_8p_top_0_mgt227_tx_p_o [get_bd_ports mgt227_tx_p_o] [get_bd_pins afcz_wrs_8p_top_0/mgt227_tx_p_o]
connect_bd_net -net afcz_wrs_8p_top_0_mgt228_tx_n_o [get_bd_ports mgt228_tx_n_o] [get_bd_pins afcz_wrs_8p_top_0/mgt228_tx_n_o]
connect_bd_net -net afcz_wrs_8p_top_0_mgt228_tx_p_o [get_bd_ports mgt228_tx_p_o] [get_bd_pins afcz_wrs_8p_top_0/mgt228_tx_p_o]
connect_bd_net -net afcz_wrs_8p_top_0_uart_txd_o [get_bd_ports uart_txd_o] [get_bd_pins afcz_wrs_8p_top_0/uart_txd_o]
connect_bd_net -net afcz_wrs_8p_top_0_wr_dac_din_o [get_bd_ports wr_dac1_din_o] [get_bd_pins afcz_wrs_8p_top_0/wr_dac_din_o]
connect_bd_net -net afcz_wrs_8p_top_0_wr_dac_sclk_o [get_bd_ports wr_dac1_sclk_o] [get_bd_pins afcz_wrs_8p_top_0/wr_dac_sclk_o]
connect_bd_net -net afcz_wrs_8p_top_0_wr_dac_sync_n_o [get_bd_ports wr_dac1_sync_n_o] [get_bd_pins afcz_wrs_8p_top_0/wr_dac_sync_n_o]
connect_bd_net -net clk_20m_vcxo_i_1 [get_bd_ports clk_20m_vcxo1_i] [get_bd_pins afcz_wrs_8p_top_0/clk_20m_vcxo_i]
connect_bd_net -net cmp_proc_sys_reset_peripheral_aresetn [get_bd_pins afcz_wrs_8p_top_0/sys_rst_n_i] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins cmp_proc_sys_reset/peripheral_aresetn]
connect_bd_net -net mgt227_rx_n_i_1 [get_bd_ports mgt227_rx_n_i] [get_bd_pins afcz_wrs_8p_top_0/mgt227_rx_n_i]
connect_bd_net -net mgt227_rx_p_i_1 [get_bd_ports mgt227_rx_p_i] [get_bd_pins afcz_wrs_8p_top_0/mgt227_rx_p_i]
connect_bd_net -net mgt228_rx_n_i_1 [get_bd_ports mgt228_rx_n_i] [get_bd_pins afcz_wrs_8p_top_0/mgt228_rx_n_i]
connect_bd_net -net mgt228_rx_p_i_1 [get_bd_ports mgt228_rx_p_i] [get_bd_pins afcz_wrs_8p_top_0/mgt228_rx_p_i]
connect_bd_net -net mgtclk1_224_n_i_1 [get_bd_ports mgtclk1_224_n_i] [get_bd_pins afcz_wrs_8p_top_0/mgtclk1_224_n_i]
connect_bd_net -net mgtclk1_224_p_i_1 [get_bd_ports mgtclk1_224_p_i] [get_bd_pins afcz_wrs_8p_top_0/mgtclk1_224_p_i]
connect_bd_net -net uart_rxd_i_0_1 [get_bd_ports uart_rxd_i] [get_bd_pins afcz_wrs_8p_top_0/uart_rxd_i]
connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins afcz_wrs_8p_top_0/clk_startup_i] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins cmp_proc_sys_reset/slowest_sync_clk] [get_bd_pins cmp_zynq/maxihpm0_fpd_aclk] [get_bd_pins cmp_zynq/pl_clk0] [get_bd_pins ila_1/clk]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins cmp_proc_sys_reset/ext_reset_in] [get_bd_pins cmp_zynq/pl_resetn0]
# Create address segments
create_bd_addr_seg -range 0x00200000 -offset 0x000400000000 [get_bd_addr_spaces cmp_zynq/Data] [get_bd_addr_segs afcz_wrs_8p_top_0/axi4l/reg0] SEG_afcz_wrs_8p_top_0_reg0
# Restore current instance
current_bd_instance $oldCurInst
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
#*****************************************************************************************
# Vivado (TM) v2018.2 (64-bit)
#
# project.tcl: Tcl script for re-creating project 'afcz_scb_8ports'
#
# Generated by Vivado on Thu Sep 28 14:08:29 CEST 2023
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
# following files are added to the source control system:-
#
# 1. This project restoration tcl script (project.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
# "/home/twl/wr-repos/wr-switch-hdl/syn/zynq_us/scb_8ports/afcz_scb_8ports/afcz_scb_8ports.srcs/sources_1/bd/top/top.bd"
# "/home/twl/wr-repos/wr-switch-hdl/syn/zynq_us/scb_8ports/afcz_scb_8ports/afcz_scb_8ports.srcs/sources_1/bd/top/hdl/top_wrapper.v"
#
# 3. The following remote source files that were added to the original project:-
#
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/utils.vh"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/dpram.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/dpram_bbs.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/lvt_1ht.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/lvt_bin.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/lvt_reg.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/mpram_lvt.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/mpram_reg.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/mrram.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/mrram_swt.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/PCK_CRC16_D16.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_shared_types_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/bare_top/wrsw_top_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/axi/axi4_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_hwiu/hwinfo_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_private_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_tru/tru_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_tru/wrsw_tru_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_tatsu/tatsu_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_tatsu/wrsw_tatsu_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/bare_top/synthesis_descriptor.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/bare_top/wrs_sdb_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rt_subsystem/wrsw_ljd_detect.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/bare_top/scb_top_bare.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_sync_register.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rt_subsystem/gen10_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rt_subsystem/gen10_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_hwiu/gw_ver_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_hwiu/hwiu_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_hwiu/hwiu_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_pstats/irq_ram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_async_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_async_grow_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_async_shrink_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_fifo_mem_cell.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_private_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_pipelined_mux.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_read_path.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_rpath_core_block.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_top.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_write_path.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_buffer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_bw_throttling.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_constants_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_descriptors_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_descriptor_manager.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_elastic_buffer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_rx_fsm.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_tx_fsm.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/pack_unpack_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_pstats/port_cntr.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_pstats/pstats_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_pstats/pstats_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_crc_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_crc.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_fast_match.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_lookup_engine.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_match.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_port_new.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_rr_arbiter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_swcore_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_alloc_resource_manager.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_ll_read_data_validation.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_multiport_linked_list.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/optimized_new_allocator/swc_multiport_page_allocator.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_ob_prio_queue.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_output_queue_scheduler.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_output_traffic_shaper.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc_ram_bug.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_pck_pg_free_module.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_pck_transfer_input.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_pck_transfer_output.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_prio_encoder.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/ram_bug/swc_rd_wr_ram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_watchdog/wdog_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_watchdog/wdog_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_wb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_pstats/wrsw_pstats.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/xswc_core.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/xswc_input_block.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/xswc_output_block_new.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/xwr_nic.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_txtsu/xwr_txtsu.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rt_subsystem/xwrsw_gen_10mhz.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_hwiu/xwrsw_hwiu.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_pstats/xwrsw_pstats.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/xwrsw_rtu_new.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_watchdog/xwrsw_watchdog.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/zynq_us/scb_8ports/afcz_wrs_8p_top.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/synth/gtwizard_ultrascale_2.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gthe4_channel_wrapper.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gtwizard_gthe4.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gtwizard_top.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_bit_sync.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/synth/gtwizard_ultrascale_v1_7_gthe4_channel.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_reset.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_reset_inv_sync.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_reset_sync.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/bare_top/wrsw_components_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_big_adder.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_reset.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/matrix_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_delay_line.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_comparator.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_word_packer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram_mixed.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_wrapper.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/example/gtwizard_ultrascale_2_example_top.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_rx_buffer_bypass.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_tx_buffer_bypass.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/example/gtwizard_ultrascale_2_example_wrapper.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_reset.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gc_reset_synchronizer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_flow_control.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_framer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rmon_counters.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/wr_nic.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/xwrsw_rtu.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_components_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/wrsw_rtu.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_port.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/mpram_xor.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_rr_arbiter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_core.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_hwiu/wrsw_hwiu.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/zynq_us/scb_8ports/timing.xdc"
# "/home/twl/wr-repos/wr-switch-hdl/top/zynq_us/scb_8ports/pins.xdc"
#
#*****************************************************************************************
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "."
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
# Set the project name
set _xil_proj_name_ "afcz_scb_8ports"
# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
set _xil_proj_name_ $::user_project_name
}
variable script_file
set script_file "project.tcl"
# Help information for this script
proc help {} {
variable script_file
puts "\nDescription:"
puts "Recreate a Vivado project from this script. The created project will be"
puts "functionally equivalent to the original project for which this script was"
puts "generated. The script contains commands for creating a project, filesets,"
puts "runs, adding/importing sources and setting properties on various objects.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file -tclargs \[--origin_dir <path>\]"
puts "$script_file -tclargs \[--project_name <name>\]"
puts "$script_file -tclargs \[--help\]\n"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
puts " origin_dir path value is \".\", otherwise, the value"
puts " that was set with the \"-paths_relative_to\" switch"
puts " when this script was generated.\n"
puts "\[--project_name <name>\] Create project with the specified name. Default"
puts " name is the name of the project from where this"
puts " script was generated.\n"
puts "\[--help\] Print help information for this script"
puts "-------------------------------------------------------------------------\n"
exit 0
}
if { $::argc > 0 } {
for {set i 0} {$i < $::argc} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
"--help" { help }
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
return 1
}
}
}
}
}
# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/"]"
# Create project
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu7ev-ffvf1517-2-e
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
# Reconstruct message rules
# None
# Set project properties
set obj [current_project]
set_property -name "board_part" -value "" -objects $obj
set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/activehdl" -objects $obj
set_property -name "compxlib.funcsim" -value "1" -objects $obj
set_property -name "compxlib.ies_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/ies" -objects $obj
set_property -name "compxlib.modelsim_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/modelsim" -objects $obj
set_property -name "compxlib.overwrite_libs" -value "0" -objects $obj
set_property -name "compxlib.questa_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/questa" -objects $obj
set_property -name "compxlib.riviera_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/riviera" -objects $obj
set_property -name "compxlib.timesim" -value "1" -objects $obj
set_property -name "compxlib.vcs_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/vcs" -objects $obj
set_property -name "compxlib.xsim_compiled_library_dir" -value "" -objects $obj
set_property -name "corecontainer.enable" -value "1" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj
set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj
set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj
set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj
set_property -name "dsa.emu_dir" -value "emu" -objects $obj
set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj
set_property -name "dsa.flash_offset_address" -value "0" -objects $obj
set_property -name "dsa.flash_size" -value "1024" -objects $obj
set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj
set_property -name "dsa.host_interface" -value "pcie" -objects $obj
set_property -name "dsa.num_compute_units" -value "60" -objects $obj
set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj
set_property -name "dsa.rom.debug_type" -value "0" -objects $obj
set_property -name "dsa.rom.prom_type" -value "0" -objects $obj
set_property -name "dsa.uses_pr" -value "1" -objects $obj
set_property -name "dsa.vendor" -value "xilinx" -objects $obj
set_property -name "dsa.version" -value "0.0" -objects $obj
set_property -name "enable_core_container" -value "1" -objects $obj
set_property -name "enable_optional_runs_sta" -value "0" -objects $obj
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
set_property -name "generate_ip_upgrade_log" -value "1" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_interface_inference_priority" -value "" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
set_property -name "part" -value "xczu7ev-ffvf1517-2-e" -objects $obj
set_property -name "project_type" -value "Default" -objects $obj
set_property -name "pr_flow" -value "0" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "sim.use_ip_compiled_libs" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "source_mgmt_mode" -value "All" -objects $obj
set_property -name "target_language" -value "Verilog" -objects $obj
set_property -name "target_simulator" -value "XSim" -objects $obj
set_property -name "tool_flow" -value "Vivado" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "6" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "6" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "6" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "6" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "6" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "6" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "6" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj
set_property -name "xsim.array_display_limit" -value "1024" -objects $obj
set_property -name "xsim.radix" -value "hex" -objects $obj
set_property -name "xsim.time_unit" -value "ns" -objects $obj
set_property -name "xsim.trace_limit" -value "65536" -objects $obj
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
source files.tcl
source bd.tcl
update_compile_order -fileset sources_1
make_wrapper -files [get_files ${origin_dir}/afcz_scb_8ports/afcz_scb_8ports.srcs/sources_1/bd/top/top.bd] -top
# Add local files from the original project (-no_copy_sources specified)
set files [list \
[file normalize "${origin_dir}/afcz_scb_8ports/afcz_scb_8ports.srcs/sources_1/bd/top/top.bd" ]\
[file normalize "${origin_dir}/afcz_scb_8ports/afcz_scb_8ports.srcs/sources_1/bd/top/hdl/top_wrapper.v" ]\
]
add_files -fileset sources_1 $files
set obj [get_filesets sources_1]
set_property -name "design_mode" -value "RTL" -objects $obj
set_property -name "edif_extra_search_paths" -value "" -objects $obj
set_property -name "elab_link_dcps" -value "1" -objects $obj
set_property -name "elab_load_timing_constraints" -value "1" -objects $obj
set_property -name "generic" -value "" -objects $obj
set_property -name "include_dirs" -value "" -objects $obj
set_property -name "lib_map_file" -value "" -objects $obj
set_property -name "loop_count" -value "1000" -objects $obj
set_property -name "name" -value "sources_1" -objects $obj
set_property -name "top" -value "top_wrapper" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "verilog_define" -value "" -objects $obj
set_property -name "verilog_uppercase" -value "0" -objects $obj
set_property -name "verilog_version" -value "verilog_2001" -objects $obj
set_property -name "vhdl_version" -value "vhdl_2k" -objects $obj
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment