... | @@ -100,15 +100,16 @@ git submodule update |
... | @@ -100,15 +100,16 @@ git submodule update |
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cd sim
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cd sim
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ln -s ../ip\_cores/wr-cores/sim wr-hdl
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ln -s ../ip\_cores/wr-cores/sim wr-hdl
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\# Enter testbench/scb\_top and generate Makefile using HDLmake (such as
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\# Enter testbench/scb\_top and generate Makefile using HDLmake
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the [Makefile](https://www.ohwr.org/2975)
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generated for me - it will not work you your PC, but can be useful to
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see)
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cd testbench/scb\_top
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cd testbench/scb\_top
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hdlmake --make-sim
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hdlmake --make-sim
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\# This should result in generation of proper Makefile, now you can
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\# This should result in generation of proper Makefile (such as the
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simulate the switch by opening ModelSim, changing the directory to
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[Makefile](https://www.ohwr.org/2975)
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generated for me - it will not work you your PC, but can be useful to
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see)
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\# Simulate the switch by opening ModelSim, changing the directory to
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testbench/scb\_top, and by running run.do script
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testbench/scb\_top, and by running run.do script
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do run.do
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do run.do
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... | @@ -169,40 +170,37 @@ The following steps are needed to simulate the switch |
... | @@ -169,40 +170,37 @@ The following steps are needed to simulate the switch |
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2. Add symbolic link in sim to wr-cores simulation drivers:
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2. Add symbolic link in sim to wr-cores simulation drivers:
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cd sim
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cd sim
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ln -s ../ip\_cores/wr-cores/sim wr-hdl
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ln -s ../ip\_cores/wr-cores/sim wr-hdl
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3. Enter testbench/scb\_top and generate Makefile using HDLmake (such
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3. Enter testbench/scb\_top and generate Makefile using HDLmake
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as the
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hdlmake --make-sim
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4. This should result in generation of proper Makefile (such as the
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[Makefile](https://www.ohwr.org/2975)
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[Makefile](https://www.ohwr.org/2975)
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generated for me - it will not work you your PC, but can be useful
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generated for me - it will not work you your PC, but can be useful
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to see)
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to see)
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cd testbench/scb\_top
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cd testbench/scb\_top
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hdlmake --make-sim
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5. Simulate by running run.do script
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4. This should result in generation of proper Makefile, now you can
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simulate by running run.do script
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do run.do
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do run.do
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5. This will probably not finish successfully since the repo does not
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6. You should see frames flowing
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contain wave.do file
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## Steps to sythesize switch HDL
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## Steps to synthesize switch HDL (master/v4)
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The following steps are needed to sythesize the switch for 18 ports
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The following steps are needed to sythesize the switch for 18 ports
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1. Clone the repo with submodules
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1. Clone the repo with submodules
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git clone --recursive
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git clone --recursive
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git:https://www.ohwr.org/white-rabbit/wr-switch-hdl.git
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git:https://www.ohwr.org/white-rabbit/wr-switch-hdl.git
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2. Add symbolic link in sim to wr-cores simulation drivers:
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2. Enter syn/scb\_8ports
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cd syn/scb\_18ports
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<!-- end list -->
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3. Generate/update ISE project by running
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hdlmake --ise-proj
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1. Enter testbench/scb\_top and generate Makefile using HDLmake (such
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4. Generate Makefile:
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as the
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hdlmake --make-ise
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5. This should result in generation of proper Makefile (such as the
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[Makefile](https://www.ohwr.org/2975)
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[Makefile](https://www.ohwr.org/2975)
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generated for me - it will not work you your PC, but can be useful
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generated for me - it will not work you your PC, but can be useful
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to see)
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to see)
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cd syn/scb\_18ports
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6. Run synthesis:
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hdlmake --make-syn
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2. Run sythesis:
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make
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make
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3. Go home, it should be ready in 4h...
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7. Go for lunch now
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