... | ... | @@ -87,30 +87,77 @@ with proper parameters. |
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The following steps are needed to simulate the switch
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1. Clone the repo with submodules
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\# Clone the repo with submodules
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git clone --recursive
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git:https://www.ohwr.org/white-rabbit/wr-switch-hdl.git
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2. Checkout tag that is compatible with v3.3 software
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\# Checkout tag that is compatible with v3.3 software
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(wr-switch-sw-v3.3) and updates submodules
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git checkout wr-switch-sw-v3.3
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git submodule update
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3. Add symbolic link in sim to wr-cores simulation drivers:
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\# Add symbolic link in sim to wr-cores simulation drivers:
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cd sim
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ln -s ../ip\_cores/wr-cores/sim wr-hdl
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4. Enter testbench/scb\_top and generate Makefile using HDLmake (such
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as the "Makefile" generated for me - it will not work you your PC,
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but can be useful to see)
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\# Enter testbench/scb\_top and generate Makefile using HDLmake (such as
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the [Makefile](https://www.ohwr.org/2973)
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generated for me - it will not work you your PC, but can be useful to
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see)
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cd testbench/scb\_top
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hdlmake --make-sim
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5. This should result in generation of proper Makefile, now you can
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\# This should result in generation of proper Makefile, now you can
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simulate the switch by opening ModelSim, changing the directory to
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testbench/scb\_top, and by running run.do script
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do run.do
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6. This will finish finish with "\# **** Error: Cannot open macro file:
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wave.do". This is because the repo does not contain wave.do file
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7. The switch does not allow traffic through due to some bugs in
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simulation, corrected in
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V4
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\# This will finish finish with "\# **** Error: Cannot open macro file:
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wave.do". This is because the repo does not contain wave.do file, so add
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a wave.do file and run again.
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\# Now you should see Ethernet frames being sent but not received ("\#
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\[port 1\] tx 32"). This is because there are 2 simulation bugs in the
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v3.3 release which needs to be fixed
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\#\# The switch does not allow traffic through due to misconfiguration
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which needs to be fixed by changing the configuration of ports in
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testbench/scb\_top/main.sv file ("rtu.set\_port\_config(dd, 1, 1, 1);"
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to "rtu.set\_port\_config(dd, 1, 1, 0);"), as described in the patch
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below:
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<code class="patch">
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@@ -236,7 +236,7 @@ module main;
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rtu.set_bus(cpu_acc, 'h60000);
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for (int dd=0;dd<g_num_ports;dd++)
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begin
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- rtu.set_port_config(dd, 1, 1, 1);
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+ rtu.set_port_config(dd, 1, 0, 1);
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end
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</code>
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\#\# There is also problem with wishbone driver, add this line (as line
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13) " m\_default\_xfer\_size = 4;" to
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sim/wr-hdl/if\_wishbone\_accessor.shv
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<code class="patch">
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index ce1958f..f98f54f 100644
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@@ -10,6 +10,7 @@ virtual class CWishboneAccessor extends CBusAccessor;
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function new();
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m_cycle_type = CLASSIC;
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+ m_default_xfer_size = 4;
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endfunction // new
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virtual task set_mode(wb_cycle_type_t mode)
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</code>
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1. now you should re-run the simulation :
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make clean
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do run.do
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2. You should see frames being forwarded by the
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switch
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### Version of HDL compatible with v4 software (currently master, once released will be wr-switch-sw-v4)
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... | ... | |