... | @@ -101,7 +101,7 @@ cd sim |
... | @@ -101,7 +101,7 @@ cd sim |
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ln -s ../ip\_cores/wr-cores/sim wr-hdl
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ln -s ../ip\_cores/wr-cores/sim wr-hdl
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\# Enter testbench/scb\_top and generate Makefile using HDLmake (such as
|
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\# Enter testbench/scb\_top and generate Makefile using HDLmake (such as
|
|
the [Makefile](https://www.ohwr.org/2973)
|
|
the [Makefile](https://www.ohwr.org/2975)
|
|
generated for me - it will not work you your PC, but can be useful to
|
|
generated for me - it will not work you your PC, but can be useful to
|
|
see)
|
|
see)
|
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cd testbench/scb\_top
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cd testbench/scb\_top
|
... | @@ -169,9 +169,9 @@ The following steps are needed to simulate the switch |
... | @@ -169,9 +169,9 @@ The following steps are needed to simulate the switch |
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2. Add symbolic link in sim to wr-cores simulation drivers:
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2. Add symbolic link in sim to wr-cores simulation drivers:
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cd sim
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cd sim
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ln -s ../ip\_cores/wr-cores/sim wr-hdl
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ln -s ../ip\_cores/wr-cores/sim wr-hdl
|
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3. Enter testbench/scb\_top and generate makefiles using HDLmake (such
|
|
3. Enter testbench/scb\_top and generate Makefile using HDLmake (such
|
|
as the
|
|
as the
|
|
[Makefile](https://www.ohwr.org/2973)
|
|
[Makefile](https://www.ohwr.org/2975)
|
|
generated for me - it will not work you your PC, but can be useful
|
|
generated for me - it will not work you your PC, but can be useful
|
|
to see)
|
|
to see)
|
|
cd testbench/scb\_top
|
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cd testbench/scb\_top
|
... | @@ -189,12 +189,20 @@ The following steps are needed to sythesize the switch for 18 ports |
... | @@ -189,12 +189,20 @@ The following steps are needed to sythesize the switch for 18 ports |
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1. Clone the repo with submodules
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1. Clone the repo with submodules
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git clone --recursive
|
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git clone --recursive
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git:https://www.ohwr.org/white-rabbit/wr-switch-hdl.git
|
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git:https://www.ohwr.org/white-rabbit/wr-switch-hdl.git
|
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2. Enter syn/scb\_18ports and generate makefiles using HDLmake
|
|
2. Add symbolic link in sim to wr-cores simulation drivers:
|
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|
|
|
|
|
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<!-- end list -->
|
|
|
|
|
|
|
|
1. Enter testbench/scb\_top and generate Makefile using HDLmake (such
|
|
|
|
as the
|
|
|
|
[Makefile](https://www.ohwr.org/2975)
|
|
|
|
generated for me - it will not work you your PC, but can be useful
|
|
|
|
to see)
|
|
cd syn/scb\_18ports
|
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cd syn/scb\_18ports
|
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hdlmake --make-syn
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hdlmake --make-syn
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3. Run sythesis:
|
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2. Run sythesis:
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make
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make
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4. Go home, it should be ready in 4h...
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3. Go home, it should be ready in 4h...
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... | | ... | |