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is used to simulate and synthesize switch HDL
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- The below explanation of the switch HDL simulation/synthesis assumes
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that you are familiar with HDLmake and use it
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- The website of the HDLmake project is [here](projects/hdl-make)
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- The website of the HDLmake project is
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[here](https://www.ohwr.org/project/hdl-make)
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- Handful information about using HDLmake can be found in Chapter
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3.4.2 of the [Getting Started with the
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SPEC](https://www.ohwr.org/project/white-rabbit/uploads/e747a4d84a62dcb0f9d784621137b003/spec-getting-started-v1.0-201403.pdf)
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... | ... | @@ -67,7 +68,7 @@ scb\_top\_sythesis.ucf. |
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The scb\_top\_sythesis.vhd instantiates top/bare\_top/scb\_top\_bare.vhd
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with proper parameters.
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## Simulation
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## Steps to run switch simulation
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(this assumes you use Linux and have HDLmake in place, otherwise good
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luck)
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... | ... | @@ -117,7 +118,7 @@ The following steps are needed to simulate the switch |
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5. This will probably not finish successfully since the repo does not
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contain wave.do file
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## Sythesis
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## Steps to sythesize switch HDL
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The following steps are needed to sythesize the switch for 18 ports
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... | ... | |