... | ... | @@ -28,8 +28,8 @@ drawing might be out of date, the general picture remains. |
|
|
|
|
|
ip\_cores - contains external cores used by the project (included in the
|
|
|
git repo as submodules)
|
|
|
modules - include specific-switch and FPGA-independent modules
|
|
|
platform - contains FPGA-dependent stuff
|
|
|
modules - include switch-specific and FPGA-independent VHDL modules
|
|
|
platform - contains FPGA-dependent VHDL code
|
|
|
sim - contains SystemVerilog modeles, drivers and register layouts used
|
|
|
by testbenches
|
|
|
syn - contains ISE project files for sythesis (e.g. if you want to
|
... | ... | |