... | ... | @@ -28,7 +28,7 @@ platform - contains FPGA-dependent stuff |
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sim - contains SystemVerilog modeles, drivers and register layouts used
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by testbenches
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syn - contains ISE project files for sythesis (e.g. if you want to
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sythesize for 18-port switch, you should go into syn/scb\_18ports)
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synthesize for 18-port switch, you should go into syn/scb\_18ports)
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testbench - contains testbenches for top-level of the switch and
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separate modules, also for a network of switches
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top - contains top-levels and constraint (UCF) files
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... | ... | @@ -38,7 +38,7 @@ top - contains top-levels and constraint (UCF) files |
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The top/bare\_top/ contains scb\_top\_bare.vhd which is a configurable
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top level entity of the switch. This entity is used by both, sythesis
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top levels and testbench of the switch. In other words, this is a
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configurable IP which needs some more VHDL to simulate or sythesize.
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configurable IP which needs some more VHDL to simulate or synthesize.
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### Switch Testbench
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... | ... | @@ -53,6 +53,20 @@ indirectly: |
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- scb\_top\_sim\_svwrap.svh is used in the main testbench:
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testbench/scb\_top/main.sv
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### Switch Synthesis
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ISE projects for switch synthesis are defined for different number of
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ports (i.e. 8, 15, and 18) in the syn directory (e.g.: syn/scb\_18ports
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for 18-switch synthesis). This is done to speed up development process:
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synthesis for 18 ports takes 4h, for 8 ports 1h, so we develop
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synthesizing for 8 ports.
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The ISE project in syn/scb\_18ports relates to the top entity and UCF
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file in top/scb\_18ports directory, i.e. scb\_top\_synthesis.vhd and
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scb\_top\_sythesis.ucf.
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The scb\_top\_sythesis.vhd instantiates top/bare\_top/scb\_top\_bare.vhd
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with proper parameters.
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## Simulation
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- We use ModelSim as a simulation tool
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