... | ... | @@ -115,41 +115,41 @@ gateware |
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## WRS gateware simulation
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The testbench of the switch is written in SystemVerilog and is located
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in testbench/scb\_top/main.sv. It uses top/bare\_top/scb\_top\_bare.vhd
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indirectly:
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in the *testbench/scb\_top/main.sv*. It uses
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*top/bare\_top/scb\_top\_bare.vhd* indirectly:
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- scb\_top\_bare.vhd is instantiated in
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top/bare\_top/scb\_top\_sim.vhd
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- scb\_top\_sim.vhd is wrapped by
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testbench/scb\_top/scb\_top\_sim\_svwrap.svh
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- scb\_top\_sim\_svwrap.svh is used in the main testbench:
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testbench/scb\_top/main.sv
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### Version of HDL compatible with v3.3 software, tag: wr-switch-sw-v3.3
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- *scb\_top\_bare.vhd* is instantiated in
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*top/bare\_top/scb\_top\_sim.vhd*
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- *scb\_top\_sim.vhd* is wrapped by
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*testbench/scb\_top/scb\_top\_sim\_svwrap.svh*
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- *scb\_top\_sim\_svwrap.svh* is used in the main testbench:
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*testbench/scb\_top/main.sv*
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The following steps are needed to simulate the switch
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\# Clone the repo with submodules
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git clone --recursive
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git:https://www.ohwr.org/white-rabbit/wr-switch-hdl.git
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\# Clone the repository with submodules (you can skip this step if
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you've already downloaded the repository for
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synthesis)
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\# Checkout tag that is compatible with v3.3 software
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(wr-switch-sw-v3.3) and updates submodules
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git checkout wr-switch-sw-v3.3
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git clone --recursive git:https://www.ohwr.org/white-rabbit/wr-switch-hdl.git
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cd wr-switch-hdl
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git submodule update
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\# Add symbolic link in sim to wr-cores simulation drivers:
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\# Add a symbolic link in the *sim* directory to *wr-cores* simulation
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drivers
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cd sim
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ln -s ../ip\_cores/wr-cores/sim wr-hdl
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ln -s ../ip_cores/wr-cores/sim wr-hdl
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\# Enter testbench/scb\_top and generate Makefile using HDLmake
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cd testbench/scb\_top
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\# Go to the main testbench location and generate a Makefile using
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*HDLmake*
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cd testbench/scb_top
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hdlmake --make-sim
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\# Most likely a scary message about dependency problem will appear. It
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can be ignored. The message is of a kind:
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\# Most likely you will see messages about dependency problem - they can
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be ignored
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<code class="shell">
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Generating makefile for simulation...
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Cannot depending file for file /home/mlipinsk/Development/new_repos/wr-switch-hdl-ni/testbench/scb_top/main.sv: simdrv_wrsw_nic.svh
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Cannot depending file for file /home/mlipinsk/Development/new_repos/wr-switch-hdl-ni/testbench/scb_top/main.sv: simdrv_txtsu.svh
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... | ... | @@ -158,85 +158,18 @@ can be ignored. The message is of a kind: |
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Cannot depending file for file /home/mlipinsk/Development/new_repos/wr-switch-hdl-ni/testbench/scb_top/main.sv: wb_packet_source.svh
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Cannot depending file for file /home/mlipinsk/Development/new_repos/wr-switch-hdl-ni/testbench/scb_top/main.sv: wb_packet_sink.svh
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Cannot depending file for file /home/mlipinsk/Development/new_repos/wr-switch-hdl-ni/testbench/scb_top/main.sv: scb_top_sim_svwrap.svh
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</code>
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\# Execution of hdlmake should result in generation of proper Makefile
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(such as the
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[Makefile](https://www.ohwr.org/2975)
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generated for me - it will not work you your PC, but can be useful to
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see)
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\# *HDLmake* should generate a proper Makefile. You should now compile
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the whole design
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make
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\# Simulate the switch by opening ModelSim, changing the directory to
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testbench/scb\_top, and by running run.do script
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do run.do
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\# This will finish finish with "\# **** Error: Cannot open macro file:
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wave.do". This is because the repo does not contain wave.do file, so add
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a wave.do file and run again.
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\# Now you should see Ethernet frames being sent but not received ("\#
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\[port 1\] tx 32"). This is because there are 2 simulation bugs in the
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v3.3 release which needs to be fixed
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\#\# The switch does not allow traffic through due to misconfiguration
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which needs to be fixed by changing the configuration of ports in
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testbench/scb\_top/main.sv file ("rtu.set\_port\_config(dd, 1, 1, 1);"
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to "rtu.set\_port\_config(dd, 1, 1, 0);"), as described in the patch
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below:
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<code class="patch">
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@@ -236,7 +236,7 @@ module main;
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rtu.set_bus(cpu_acc, 'h60000);
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for (int dd=0;dd<g_num_ports;dd++)
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begin
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- rtu.set_port_config(dd, 1, 1, 1);
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+ rtu.set_port_config(dd, 1, 0, 1);
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end
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</code>
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\#\# There is also problem with wishbone driver, add this line (as line
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13) " m\_default\_xfer\_size = 4;" to
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sim/wr-hdl/if\_wishbone\_accessor.shv
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<code class="patch">
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index ce1958f..f98f54f 100644
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@@ -10,6 +10,7 @@ virtual class CWishboneAccessor extends CBusAccessor;
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function new();
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m_cycle_type = CLASSIC;
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+ m_default_xfer_size = 4;
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endfunction // new
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virtual task set_mode(wb_cycle_type_t mode)
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</code>
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1. now you should re-run the simulation :
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make clean
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do run.do
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2. You should see frames being forwarded by the
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switch
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### Version of HDL compatible with v4 software (currently master, once released will be wr-switch-sw-v4)
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The following steps are needed to simulate the switch
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1. Clone the repo with submodules
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git clone --recursive
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git:https://www.ohwr.org/white-rabbit/wr-switch-hdl.git
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2. Add symbolic link in sim to wr-cores simulation drivers:
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cd sim
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ln -s ../ip\_cores/wr-cores/sim wr-hdl
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3. Enter testbench/scb\_top and generate Makefile using HDLmake
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hdlmake --make-sim
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4. This should result in generation of proper Makefile (such as the
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[Makefile](https://www.ohwr.org/2976)
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generated for me - it will not work you your PC, but can be useful
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to see)
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cd testbench/scb\_top
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5. Simulate by running run.do script
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do run.do
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6. You should see frames flowing
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1. You should see frames being forwarded by the switch
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-----
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