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# For Developers
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Here is some information for people who want to contribute to the
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development of switch's HDL. Note that we use HDLmake tool to make our
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life easier. An unfinished drawing of the architecture of switch HDL is
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This page provide information for people who want to contribute to the
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development of switch's HDL. It is meant to explain first steps to get
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going with simulation and synthesis assuming a developer
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uses HDLmake (explained below) and Linux PC.
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An sketch (unfinished) depicting architecture of switch HDL can be found
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[here](https://www.ohwr.org/project/wr-switch-hdl/uploads/63a1d6b10a371fb27f72cb6c5b41ac3c/SwitchGWarchitecture.jpg).
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Note that the switch is under development and some details of the
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drawing might be out of date, the general picture remains.
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The figure provides a high level of details when zoomed in; while when
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zoomed out, it should be handy in getting a global idea of HDL
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architecture. Note that the switch is under development and some details
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of the drawing might be out of date, the general picture remains.
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HDLmake tool is used for WR switch HDL development to make developers'
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life easier.
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## HDLmake
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- Tool for generating multi-purpose makefiles for FPGA projects that
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is used to simulate and synthesize switch HDL
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- It is a tool for generating multi-purpose makefiles for FPGA
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projects that is used to simulate and synthesize switch HDL
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- The below explanation of the switch HDL simulation/synthesis assumes
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that you are familiar with HDLmake and use it
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that you are familiar with HDLmake, have it installed, added to your
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PATH and can use it.
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- The website of the HDLmake project is
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[here](https://www.ohwr.org/project/hdl-make)
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- Handful information about using HDLmake can be found in Chapter
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... | ... | @@ -20,7 +29,7 @@ drawing might be out of date, the general picture remains. |
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SPEC](https://www.ohwr.org/project/white-rabbit/uploads/e747a4d84a62dcb0f9d784621137b003/spec-getting-started-v1.0-201403.pdf)
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tutorial that is part of [Getting Started with
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SPEC](https://www.ohwr.org/project/spec-getting-started) project
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- Beware: we are currently using ISYP branch of the HDLmake
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- Beware: we are currently using ISYP branch of HDLmake
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## HDL directory structure
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... | ... | @@ -28,27 +37,27 @@ drawing might be out of date, the general picture remains. |
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ip\_cores - contains external cores used by the project (included in the
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git repo as submodules)
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modules - include switch-specific and FPGA-independent VHDL modules
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modules - include switch-specific & FPGA-independent VHDL modules
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platform - contains FPGA-dependent VHDL code
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sim - contains SystemVerilog modeles, drivers and register layouts used
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sim - contains SystemVerilog models, drivers and register layouts used
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by testbenches
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syn - contains ISE project files for sythesis (e.g. if you want to
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syn - contains ISE project files for synthesis (e.g. if you want to
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synthesize for 18-port switch, you should go into syn/scb\_18ports)
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testbench - contains testbenches for top-level of the switch and
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separate modules, also for a network of switches
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testbench - contains testbenches for top-level of the switch and some
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modules, also for a network of switches
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top - contains top-levels and constraint (UCF) files
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-----
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The top/bare\_top/ contains scb\_top\_bare.vhd which is a configurable
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top level entity of the switch. This entity is used by both, sythesis
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top levels and testbench of the switch. In other words, this is a
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configurable IP which needs some more VHDL to simulate or synthesize.
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top level entity of the switch. This entity is used by both, synthesis
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and testbench top levels. In other words, this is a configurable IP
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which needs some more VHDL to simulate or synthesize.
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### Switch Testbench
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The testbench of the switch is written in SystemVerilog and contained in
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testbench/scb\_top/main.sv. It uses top/bare\_top/scb\_top\_bare.vhd
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The testbench of the switch is written in SystemVerilog and is located
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in testbench/scb\_top/main.sv. It uses top/bare\_top/scb\_top\_bare.vhd
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indirectly:
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- scb\_top\_bare.vhd is instantiated in
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... | ... | @@ -62,21 +71,18 @@ indirectly: |
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ISE projects for switch synthesis are defined for different number of
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ports (i.e. 8, 15, and 18) in the syn directory (e.g.: syn/scb\_18ports
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for 18-switch synthesis). This is done to speed up development process:
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synthesis for 18 ports takes 4h, for 8 ports 1h, so we develop
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synthesizing for 8 ports.
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for 18-switch synthesis). We synthesize for 8 ports to speed up
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development process: synthesis for 18 ports takes 4h, for 8 ports 1h, so
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we develop synthesizing for 8 ports.
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The ISE project in syn/scb\_18ports relates to the top entity and UCF
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file in top/scb\_18ports directory, i.e. scb\_top\_synthesis.vhd and
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files in top/scb\_18ports directory, i.e. scb\_top\_synthesis.vhd and
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scb\_top\_sythesis.ucf.
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The scb\_top\_sythesis.vhd instantiates top/bare\_top/scb\_top\_bare.vhd
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with proper parameters.
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## Steps to run switch simulation
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(this assumes you use Linux and have HDLmake in place, otherwise good
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luck)
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### Version of HDL compatible with v3.3 software, tag: wr-switch-sw-v3.3
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The following steps are needed to simulate the switch
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